Remove GHC's haskell98 dependency

[ghc-hetmet.git] / includes / SMP.h

diff --git a/includes/SMP.h b/includes/SMP.h
index 49bc336..7592abb 100644 (file)
--- a/includes/SMP.h
+++ b/includes/SMP.h
@@ -18,7 +18,7 @@
 
 #if defined(THREADED_RTS)
 
-#if  defined(TICKY_TICKY)
+#if defined(TICKY_TICKY)
 #error Build options incompatible with THREADED_RTS.
 #endif
 
@@ -52,18 +52,43 @@ EXTERN_INLINE StgWord xchg(StgPtr p, StgWord w);
  */
 EXTERN_INLINE StgWord cas(StgVolatilePtr p, StgWord o, StgWord n);
 
+/*
+ * Atomic increment
+ *
+ * atomic_inc(p) {
+ *   return ++(*p);
+ * }
+ */
+EXTERN_INLINE StgWord atomic_inc(StgVolatilePtr p);
+
+/*
+ * Atomic decrement
+ *
+ * atomic_dec(p) {
+ *   return --(*p);
+ * }
+ */
+EXTERN_INLINE StgWord atomic_dec(StgVolatilePtr p);
+
 #endif // !IN_STG_CODE
 
 /*
- * Prevents write operations from moving across this call in either
- * direction.
+ * Various kinds of memory barrier.
+ *  write_barrier: prevents future stores occurring before prededing stores.
+ *  store_load_barrier: prevents future loads occurring before preceding stores.
+ *  load_load_barrier: prevents future loads occurring before earlier stores.
+ *
+ * Reference for these: "The JSR-133 Cookbook for Compiler Writers"
+ * http://gee.cs.oswego.edu/dl/jmm/cookbook.html
+ *
+ * To check whether you got these right, try the test in 
+ *   testsuite/tests/ghc-regress/rts/testwsdeque.c
+ * This tests the work-stealing deque implementation, which relies on
+ * properly working store_load and load_load memory barriers.
  */ 
 EXTERN_INLINE void write_barrier(void);
-
-/*
- * Prevents loads from moving before earlier stores.
- */
 EXTERN_INLINE void store_load_barrier(void);
+EXTERN_INLINE void load_load_barrier(void);
 
 /* ----------------------------------------------------------------------------
    Implementations
@@ -157,17 +182,55 @@ cas(StgVolatilePtr p, StgWord o, StgWord n)
 #endif
 }
 
+EXTERN_INLINE StgWord
+atomic_inc(StgVolatilePtr p)
+{
+#if 0 // defined(i386_HOST_ARCH) || defined(x86_64_HOST_ARCH)
+    StgWord r;
+    r = 1;
+    __asm__ __volatile__ (
+        "lock\nxadd %0,%1":
+            "+r" (r), "+m" (*p):
+    );
+    return r;
+#else
+    StgWord old, new;
+    do {
+        old = *p;
+        new = old + 1;
+    } while (cas(p, old, new) != old);
+    return new;
+#endif
+}
+
+EXTERN_INLINE StgWord
+atomic_dec(StgVolatilePtr p)
+{
+#if 0 //defined(i386_HOST_ARCH) || defined(x86_64_HOST_ARCH)
+    StgWord r;
+    r = (StgWord)-1;
+    __asm__ __volatile__ (
+        "lock\nxadd %0,%1":
+            "+r" (r), "+m" (*p):
+    );
+    return r;
+#else
+    StgWord old, new;
+    do {
+        old = *p;
+        new = old - 1;
+    } while (cas(p, old, new) != old);
+    return new;
+#endif
+}
+
 #endif // !IN_STG_CODE
 
 /*
- * Write barrier - ensure that all preceding writes have happened
- * before all following writes.  
- *
- * We need to tell both the compiler AND the CPU about the barrier.
- * This is a brute force solution; better results might be obtained by
- * using volatile type declarations to get fine-grained ordering
- * control in C, and optionally a memory barrier instruction on CPUs
- * that require it (not x86 or x86_64).
+ * We need to tell both the compiler AND the CPU about the barriers.
+ * It's no good preventing the CPU from reordering the operations if
+ * the compiler has already done so - hence the "memory" restriction
+ * on each of the barriers below.
  */
 EXTERN_INLINE void
 write_barrier(void) {
@@ -176,7 +239,7 @@ write_barrier(void) {
 #elif powerpc_HOST_ARCH
     __asm__ __volatile__ ("lwsync" : : : "memory");
 #elif sparc_HOST_ARCH
-    /* Sparc in TSO mode does not require write/write barriers. */
+    /* Sparc in TSO mode does not require store/store barriers. */
     __asm__ __volatile__ ("" : : : "memory");
 #elif !defined(WITHSMP)
     return;
@@ -192,10 +255,27 @@ store_load_barrier(void) {
 #elif x86_64_HOST_ARCH
     __asm__ __volatile__ ("lock; addq $0,0(%%rsp)" : : : "memory");
 #elif powerpc_HOST_ARCH
-    __asm__ __volatile__ ("msync" : : : "memory");
+    __asm__ __volatile__ ("sync" : : : "memory");
+#elif sparc_HOST_ARCH
+    __asm__ __volatile__ ("membar #StoreLoad" : : : "memory");
+#elif !defined(WITHSMP)
+    return;
+#else
+#error memory barriers unimplemented on this architecture
+#endif
+}
+
+EXTERN_INLINE void
+load_load_barrier(void) {
+#if i386_HOST_ARCH
+    __asm__ __volatile__ ("" : : : "memory");
+#elif x86_64_HOST_ARCH
+    __asm__ __volatile__ ("" : : : "memory");
+#elif powerpc_HOST_ARCH
+    __asm__ __volatile__ ("lwsync" : : : "memory");
 #elif sparc_HOST_ARCH
-    /* Sparc in TSO mode does not require write/write barriers. */
-    __asm__ __volatile__ ("membar" : : : "memory");
+    /* Sparc in TSO mode does not require load/load barriers. */
+    __asm__ __volatile__ ("" : : : "memory");
 #elif !defined(WITHSMP)
     return;
 #else
@@ -206,9 +286,9 @@ store_load_barrier(void) {
 /* ---------------------------------------------------------------------- */
 #else /* !THREADED_RTS */
 
-#define write_barrier() /* nothing */
-
+#define write_barrier()      /* nothing */
 #define store_load_barrier() /* nothing */
+#define load_load_barrier()  /* nothing */
 
 INLINE_HEADER StgWord
 xchg(StgPtr p, StgWord w)
@@ -229,6 +309,18 @@ cas(StgVolatilePtr p, StgWord o, StgWord n)
     return result;
 }
 
+INLINE_HEADER StgWord
+atomic_inc(StgVolatilePtr p)
+{
+    return ++(*p);
+}
+
+INLINE_HEADER StgWord
+atomic_dec(StgVolatilePtr p)
+{
+    return --(*p);
+}
+
 #endif /* !THREADED_RTS */
 
 #endif /* SMP_H */