:"=r" (result)
:"r" (w), "r" (p)
);
+#elif sparc_HOST_ARCH
+ result = w;
+ __asm__ __volatile__ (
+ "swap %1,%0"
+ : "+r" (result), "+m" (*p)
+ : /* no input-only operands */
+ );
+#elif !defined(WITHSMP)
+ result = *p;
+ *p = w;
#else
#error xchg() unimplemented on this architecture
#endif
:"cc", "memory"
);
return result;
+#elif sparc_HOST_ARCH
+ __asm__ __volatile__ (
+ "cas [%1], %2, %0"
+ : "+r" (n)
+ : "r" (p), "r" (o)
+ : "memory"
+ );
+ return n;
+#elif !defined(WITHSMP)
+ StgWord result;
+ result = *p;
+ if (result == o) {
+ *p = n;
+ }
+ return result;
#else
#error cas() unimplemented on this architecture
#endif
__asm__ __volatile__ ("" : : : "memory");
#elif powerpc_HOST_ARCH
__asm__ __volatile__ ("lwsync" : : : "memory");
+#elif sparc_HOST_ARCH
+ /* Sparc in TSO mode does not require write/write barriers. */
+ __asm__ __volatile__ ("" : : : "memory");
+#elif !defined(WITHSMP)
+ return;
#else
#error memory barriers unimplemented on this architecture
#endif
INLINE_HEADER StgInfoTable *
lockClosure(StgClosure *p)
{
-#if i386_HOST_ARCH || x86_64_HOST_ARCH || powerpc_HOST_ARCH
StgWord info;
do {
nat i = 0;
} while (++i < SPIN_COUNT);
yieldThread();
} while (1);
-#else
- ACQUIRE_SM_LOCK
-#endif
}
INLINE_HEADER void
unlockClosure(StgClosure *p, StgInfoTable *info)
{
-#if i386_HOST_ARCH || x86_64_HOST_ARCH || powerpc_HOST_ARCH
// This is a strictly ordered write, so we need a wb():
write_barrier();
p->header.info = info;
-#else
- RELEASE_SM_LOCK;
-#endif
}
#else /* !THREADED_RTS */