* Unregisterised builds are ok, but only 1 CPU supported.
*/
-#ifdef CMINUSMINUS
-
-#define unlockClosure(ptr,info) \
- prim %write_barrier() []; \
- StgHeader_info(ptr) = info;
-
-#else
-
#if defined(THREADED_RTS)
#if defined(TICKY_TICKY)
Atomic operations
------------------------------------------------------------------------- */
+#if !IN_STG_CODE
+// We only want write_barrier() declared in .hc files. Defining the
+// other inline functions here causes type mismatch errors from gcc,
+// because the generated C code is assuming that there are no
+// prototypes in scope.
+
/*
* The atomic exchange operation: xchg(p,w) exchanges the value
* pointed to by p with the value w, returning the old value.
* Used for locking closures during updates (see lockClosure() below)
* and the MVar primops.
*/
-INLINE_HEADER StgWord xchg(StgPtr p, StgWord w);
+EXTERN_INLINE StgWord xchg(StgPtr p, StgWord w);
/*
* Compare-and-swap. Atomically does this:
* return r;
* }
*/
-INLINE_HEADER StgWord cas(StgVolatilePtr p, StgWord o, StgWord n);
+EXTERN_INLINE StgWord cas(StgVolatilePtr p, StgWord o, StgWord n);
+
+#endif // !IN_STG_CODE
/*
* Prevents write operations from moving across this call in either
* direction.
*/
-INLINE_HEADER void write_barrier(void);
+EXTERN_INLINE void write_barrier(void);
/* ----------------------------------------------------------------------------
Implementations
------------------------------------------------------------------------- */
+
+#if !IN_STG_CODE
+
/*
* NB: the xchg instruction is implicitly locked, so we do not need
* a lock prefix here.
*/
-INLINE_HEADER StgWord
+EXTERN_INLINE StgWord
xchg(StgPtr p, StgWord w)
{
StgWord result;
* CMPXCHG - the single-word atomic compare-and-exchange instruction. Used
* in the STM implementation.
*/
-INLINE_HEADER StgWord
+EXTERN_INLINE StgWord
cas(StgVolatilePtr p, StgWord o, StgWord n)
{
#if i386_HOST_ARCH || x86_64_HOST_ARCH
#endif
}
+#endif // !IN_STG_CODE
+
/*
* Write barrier - ensure that all preceding writes have happened
* before all following writes.
* control in C, and optionally a memory barrier instruction on CPUs
* that require it (not x86 or x86_64).
*/
-INLINE_HEADER void
+EXTERN_INLINE void
write_barrier(void) {
#if i386_HOST_ARCH || x86_64_HOST_ARCH
__asm__ __volatile__ ("" : : : "memory");
#endif /* !THREADED_RTS */
-#endif /* CMINUSMINUS */
-
#endif /* SMP_H */