== TeX ==============================================================
-This ship implements a 3-input {\bf L}ook {\bf U}p {\bf T}able. The
-least significant eight bits of the {\tt inLut} value form a truth
-table with three inputs and one output.
+This ship implements a bitwise 3-input {\bf L}ook {\bf U}p {\bf
+T}able. The least significant eight bits of the {\tt inLut} value
+form a truth table with three inputs and one output.
When values are available at all four inputs they are consumed and a
value is produced at {\tt out}. Each bit of {\tt out} is produced by
as a bit index into {\tt inLut}'s value (whose least significant bit
is considered ``bit zero'').
-The ship-specific constants refer to commonly-used truth tables for
-{\it two-input} functions; these constant truth tables are invariant
-under input {\tt in3}.
== Fleeterpreter ====================================================
public void service() {
== FleetSim ==============================================================
== FPGA ==============================================================
- reg have_in1;
- reg [(`DATAWIDTH-1):0] reg_in1;
- reg have_in2;
- reg [(`DATAWIDTH-1):0] reg_in2;
- reg have_in3;
- reg [(`DATAWIDTH-1):0] reg_in3;
- reg have_inLut;
- reg [(`DATAWIDTH-1):0] reg_inLut;
+ reg out_draining;
+ wire [7:0] lut;
- wire [(`DATAWIDTH-1):0] out;
genvar i;
generate
- for(i=0; i<`DATAWIDTH; i=i+1) begin : OUT
- assign out[i] = reg_inLut[{reg_in3[i], reg_in2[i], reg_in1[i]}];
+ for(i=0; i<`WORDWIDTH; i=i+1) begin : OUT
+ assign out_d_[i] = lut[{in3_d[i], in2_d[i], in1_d[i]}];
end
endgenerate
+ assign lut = inLut_d[7:0];
+
always @(posedge clk) begin
- if (!have_in1) begin
- `onread(in1_r, in1_a) have_in1 = 1; reg_in1 = in1_d; end
- end else
- if (!have_in2) begin
- `onread(in2_r, in2_a) have_in2 = 1; reg_in2 = in2_d; end
- end else
- if (!have_in3) begin
- `onread(in3_r, in3_a) have_in3 = 1; reg_in3 = in3_d; end
- end else
- if (!have_inLut) begin
- `onread(inLut_r, inLut_a) have_inLut = 1; reg_inLut = inLut_d; end
- end else
-
- if (have_in1 && have_in2 && have_in3 && have_inLut) begin
- out_d = out;
- `onwrite(out_r, out_a)
- have_in1 = 0;
- have_in2 = 0;
- have_in3 = 0;
- have_inLut = 0;
+ if (rst) begin
+ `reset
+ out_draining <= 0;
+ end else begin
+ `cleanup
+ if (out_draining && `out_empty) begin
+ `drain_in1
+ `drain_in2
+ `drain_in3
+ `drain_inLut
+ out_draining <= 0;
+ end
+ if (!out_draining && `in1_full && `in2_full && `in3_full && `inLut_full && `out_empty) begin
+ `fill_out
+ out_draining <= 1;
end
end
end
#ship debug : Debug
#ship lut : Lut3
-#ship alu : Alu1
+#ship alu : Alu
-lut.in1: literal 85; [*] deliver;
-lut.in2: literal 51; [*] deliver;
-lut.in3: literal 15; [*] deliver;
-lut.out: [*] take, sendto debug.in;
+lut.in1: set word= 85; set ilc=*; deliver;
+lut.in2: set word= 51; set ilc=*; deliver;
+lut.in3: set word= 15; set ilc=*; deliver;
+lut.out: set ilc=*; collect, send to debug.in;
// cycle through truth tables using alu as INC
+alu.in2:
+ set word= 1;
+ set ilc=*; deliver;
alu.inOp:
- literal 1;
- [120] deliver;
- [120] deliver;
- [15] deliver;
-alu.in:
- literal 0;
+ set word= Alu.inOp[ADD];
+ set ilc=*; deliver;
+alu.in1:
+ set word= 0;
deliver;
- [*] take, deliver;
+ set ilc=*; recv, deliver;
alu.out:
- clog;
- (*) wait, take, sendto lut.inLut;
- (*) sendto alu.in;
- unclog;
-
-// acks from debug ship trigger new truth tables
-debug.in:
- [*] take, deliver, notify alu.out;
+ set olc=2;
+ head;
+ recv token, collect, send to lut.inLut;
+ send to alu.in1;
+ tail;
lut.inLut:
- literal 0;
+ set word= 0;
deliver;
- [*] take, deliver;
+ set ilc=*; recv, deliver;
+// acks from debug ship trigger new truth tables
+debug.in:
+ set ilc=63;
+ recv, deliver, send token to alu.out;
+ set ilc=63;
+ recv, deliver, send token to alu.out;
+ set ilc=63;
+ recv, deliver, send token to alu.out;
+ set ilc=63;
+ recv, deliver, send token to alu.out;
+ set ilc=4;
+ recv, deliver, send token to alu.out;