X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;ds=sidebyside;f=chips%2Ff2%2Fdoc%2Fam42%2Fam42.tex;h=a85e8259f340e23b719acd6fa3b30fed86dde0b9;hb=5eb7f853e3ab759d063ed8ca3196a7b17501214f;hp=c6194ef15c872f38485ab809a312d58d88fb6db4;hpb=da7ca578539d281cc67255276f7d02a537f71f66;p=fleet.git diff --git a/chips/f2/doc/am42/am42.tex b/chips/f2/doc/am42/am42.tex index c6194ef..a85e825 100644 --- a/chips/f2/doc/am42/am42.tex +++ b/chips/f2/doc/am42/am42.tex @@ -29,14 +29,13 @@ To Do: \begin{verbatim} - - tokenhood as address bit - - signal/path boundary/etc + - tokenhood as address bit + - signal/path boundary/etc - Rename EPI and OD to something more meaningful - Get rid of OD? - get rid of shadow latch - single counter - figure out C-flag / signal bit situation - - single "predicate" flag - Suggestion that there should be a "T" flag - Get rid of "shadow latch" for literals? - unify flags and signal bit by saying that the dock can @@ -49,6 +48,18 @@ To Do: - Simplify the whole c-flag/signal-bit situation - tokenhood should be LITERALLY an address bit! + - kinds of data: + - ship-to-ship data (words) + - dock-to-dock data (signal bits) + - ship-to-dock data (c-flag) + - dock-to-ship data (flushing/bonus bit) + - sources of these: + - instruction stream + - ship word (at output dock) + - ship extras + - packet word (at input dock) + - packet signal bit + \end{verbatim} \begin{tabular}{rl} @@ -196,8 +207,14 @@ The dock has four flags: {\tt A}, {\tt B}, {\tt C}, and {\tt Z}. ship or from an inbound packet. See the {\tt move} instruction for further details. -\item The {\tt Z}\ flag is known as the - {\it zero}\ flag. The {\tt +\item The {\tt P} flag is used for predication; see the next section + for details. When a torpedo strikes or the counter is + decremented from any value to zero, the {\tt P} flag is cleared. + The {\tt P} flag may also be set and cleared by the {\tt set} + instruction. + +\item The {\tt Z} flag is known as the + {\it zero} flag. The {\tt Z}\ flag is {\it set} whenever the {\tt LC} is zero. In an actual implementation the {\tt Z}\ flag might require an actual latch; it might simply be derived @@ -207,41 +224,22 @@ The dock has four flags: {\tt A}, {\tt B}, {\tt C}, and {\tt Z}. \subsection{Predication} -All instructions except for {\tt head} and {\tt tail} have a three-bit -field marked {\tt P}, which specifies a {\it predicate}. +All instructions except for {\tt head} and {\tt tail} have a bit +marked {\tt U}, for {\it unconditional}. An instruction with the {\tt + U} bit set always executes. An instruction with the {\tt U} bit +cleared will execute {\it only if the {\tt P} flag is set}. \begin{center} \setlength{\bitwidth}{5mm} {\tt{\footnotesize{ \begin{bytefield}{25} - \bitheader[b]{0,21,22,24}\\ - \bitbox{3}{P} - \bitbox[tbr]{22}{} - + \bitheader[b]{0,24}\\ + \bitbox{1}{U} + \bitbox[tbr]{24}{} \end{bytefield}}}} \end{center} -The predicate determines which conditions must be true in order for -the instruction to execute; if it is not executed, it is simply {\it - ignored}. The table below shows what conditions must be true in -order for an instruction to execute: - -\begin{center} -\begin{tabular}{|r|l|}\hline -Code & Execute if \\\hline -{\tt 000:} & {\tt Z=0}\ and {\tt A=0} \\ -{\tt 001:} & {\tt Z=0}\ and {\tt A=1} \\ -{\tt 010:} & {\tt Z=0}\ and {\tt B=0} \\ -{\tt 011:} & {\tt Z=0}\ and {\tt B=1} \\ -{\tt 100:} & Unused \\ -{\tt 101:} & {\tt Z=1}\ \\ -{\tt 110:} & {\tt Z=0}\ \\ -{\tt 111:} & always \\ -\hline\end{tabular} -\end{center} - \pagebreak - \subsection{The Requeue Stage} The requeue stage has two inputs, which will be referred to as the @@ -292,8 +290,8 @@ output. When an {\tt abort} instruction is executed, the requeue stage transitions back to the {\sc Updating} state. Note that {\tt abort} -instructions include a predicate; an {\tt abort} instruction whose -predicate is not met will not cause this transition. +instructions include a {\tt U} bit -- an {\tt abort} instruction with that bit set +will not cause this transition when the {\tt P} flag is cleared. @@ -308,18 +306,19 @@ predicate is not met will not cause this transition. \begin{bytefield}{25} \bitheader[b]{14-21}\\ \color{light} - \bitbox{3}{P} - - + \bitbox{1}{U} + \bitbox{1}{} + \bitbox{1}{} +\color{black} \bitbox{1}{0} \bitbox{1}{R} \bitbox{1}{I} + \bitbox{1}{S} - \bitbox{1}{\tt Ti} - \bitbox{1}{\tt Di} + \bitbox{1}{\tt Fi} + \bitbox{1}{\tt Sh} \bitbox{1}{\tt Dc} - \bitbox{1}{\tt Do} - \bitbox{1}{\tt To} + \bitbox{1}{\tt Fo} \bitbox[l]{19}{} \end{bytefield}} @@ -355,32 +354,25 @@ predicate is not met will not cause this transition. \bitsMove \begin{itemize} -\item {\tt Ti} - Token Input: wait for the token predecessor to be full and drain it. -\item {\tt Di} - Data Input: wait for the data predecessor to be full and drain it. +\item {\tt Fi} - Fabric input: wait for fabric predecessor to be full and drain it. +\item {\tt Fo} - Fabric output: wait for fabric successor to be empty and fill it. \item {\tt Dc} - Data Capture: pulse the data latch. -\item {\tt Do} - Data Output: fill the data successor. -\item {\tt To} - Token Output: fill the token successor. +\item {\tt Sh} - Ship: at an input/output dock, wait for the ship successor/predecessor to be empty/full and fill/drain it. \end{itemize} -The data successor and token successor must both be empty in order for -a {\tt move} instruction to attempt execution. +The fabric successor must be empty in order for a {\tt move} +instruction to attempt execution. - -If the {\tt S} bit is set (not shown -- there is no space left!), the -{\tt move} instruction will subtract one from the {\tt LC} counter -each time it executes. -NOTE: the flavor of {\tt set} instruction which decrements the counter -is now unnecessary; we can simply use a ``do-nothing {\tt move}'' with -the {\tt S}-bit set for that. +If the {\tt S} bit is set, the {\tt move} instruction will subtract +one from the {\tt LC} counter each time it executes. An instruction +with only this bit set (and no other) takes the place of the dedicated +``decrement OLC'' instruction in previous designs. If the {\tt R} bit is set, the {\tt move} instruction will execute repeatedly until its predicate no longer holds (or a torpedo strikes). An ``infinite'' or ``standing'' move can be achieved by setting the {\tt R} bit and clearing the {\tt S} bit. - -\subsection*{Torpedoes} - The {\tt I} bit stands for {\tt Immune}, and indicates if the instruction is immune to torpedoes. If a {\tt move} instruction which is not immune is waiting to execute and a torpedo is lying in wait, @@ -451,7 +443,9 @@ loop counter. {\tt\begin{bytefield}{25} \bitheader[b]{19-21}\\ \color{light} - \bitbox{3}{P} + \bitbox{1}{U} + \bitbox{1}{} + \bitbox{1}{} \bitbox{1}{1} \bitbox{1}{0} \bitbox{1}{1} @@ -566,7 +560,9 @@ into the data latch \shiftImmediateSize\ bits at a time. \begin{bytefield}{25} \bitheader[b]{0,18-21}\\ \color{light} - \bitbox{3}{P} + \bitbox{1}{U} + \bitbox{1}{} + \bitbox{1}{} \bitbox{1}{1} @@ -576,7 +572,7 @@ into the data latch \shiftImmediateSize\ bits at a time. \bitbox{\shiftImmediateSize}{Immediate} \end{bytefield}} } -%\bitsShift +\bitsShift The FleetTwo implementation is likely to have an unarchitected ``literal latch'' at the on deck ({\tt OD}) stage, which is loaded @@ -592,7 +588,9 @@ the instruction executes. \begin{bytefield}{25} \bitheader[b]{18-21}\\ \color{light} - \bitbox{3}{P} + \bitbox{1}{U} + \bitbox{1}{} + \bitbox{1}{} \bitbox{1}{1} @@ -661,14 +659,14 @@ the Requeue Stage for further details. \vspace{3mm}\hspace{-1cm}{\tt move}\hspace{1cm}\vspace{-6mm}\\ -%\bitsMove +\bitsMove \bitsFlush \vspace{3mm}\hspace{-1cm}{\tt shift}\hspace{1cm}\vspace{-6mm}\\ \bitsShift \vspace{3mm}\hspace{-1cm}{\tt set}\hspace{1cm}\vspace{-6mm}\\ -%\bitsSet +\bitsSet \vspace{3mm}\hspace{-1cm}{\tt abort}\hspace{1cm}\vspace{-6mm}\\ \bitsAbort