X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;ds=sidebyside;f=chips%2Fmarina%2Felectric%2FdukeF.delib%2FinvQx4.lay;fp=chips%2Fmarina%2Felectric%2FdukeF.delib%2FinvQx4.lay;h=d9db1aeccedc2490472d8de500d005ccb009d1d3;hb=8ae5f0096902dbf7a528382a45861c8c74693c40;hp=0000000000000000000000000000000000000000;hpb=4e6d6c048a89a60bade6508938706b729847cf95;p=fleet.git

diff --git a/chips/marina/electric/dukeF.delib/invQx4.lay b/chips/marina/electric/dukeF.delib/invQx4.lay
new file mode 100644
index 0000000..d9db1ae
--- /dev/null
+++ b/chips/marina/electric/dukeF.delib/invQx4.lay
@@ -0,0 +1,46 @@
+HdukeF|8.10k
+
+# Cell invQx4;1{lay}
+CinvQx4;1{lay}||cmos90|1184003385045|1240848417057|I|ATTR_NCC(D5G3;NTY210;)S["exportsConnectedByParent vdd /vdd_[0-9]+/","exportsConnectedByParent gnd /gnd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1243262533078
+Ngeneric:Facet-Center|art@0||0|0||||AV
+IinvQ;1{lay}|invQ@0||0|0|Y||D5G4;
+IinvQ;1{lay}|invQ@1||0|144|XY||D5G4;
+IinvQ;1{lay}|invQ@2||0|288|XY||D5G4;
+IinvQ;1{lay}|invQ@3||0|432|XY||D5G4;
+NMetal-1-Pin|pin@0||-8|72||||
+NMetal-1-Pin|pin@2||-6|72||||
+Ametal-1|net@0|||S900|invQ@1|in|-8|120|pin@0||-8|72
+Ametal-1|net@2|||S1800|pin@0||-8|72|pin@2||-6|72
+Ametal-1|net@3|||S2700|invQ@0|out|-6|-24|pin@2||-6|72
+Ametal-1|net@6|||S0|invQ@1|out|6|120|invQ@1|out|6|120
+Ametal-1|net@7|||S0|invQ@2|out|6|264|invQ@2|out|6|264
+Ametal-1|net@8|||S900|invQ@2|in|-8|264|invQ@1|in|-8|120
+Ametal-1|net@9|||S0|invQ@3|out|6|408|invQ@3|out|6|408
+Ametal-1|net@10|||S900|invQ@3|in|-8|408|invQ@2|in|-8|264
+Egnd||D5G2;|invQ@0|gnd|G
+Egnd_1||D5G2;|invQ@0|gnd_1|G
+Egnd_2||D5G2;|invQ@1|gnd|G
+Egnd_3||D5G2;|invQ@1|gnd_1|G
+Egnd_4||D5G2;|invQ@2|gnd|G
+Egnd_5||D5G2;|invQ@2|gnd_1|G
+Egnd_6||D5G2;|invQ@3|gnd|G
+Egnd_7||D5G2;|invQ@3|gnd_1|G
+Ein||D5G2;|invQ@0|in|I
+Eout||D5G2;|invQ@0|out|O
+Evdd||D5G2;|invQ@0|vdd|P
+Evdd_1||D5G2;|invQ@0|vdd_1|P
+Evdd_2||D5G2;|invQ@0|vdd_2|P
+Evdd_3||D5G2;|invQ@0|vdd_3|P
+Evdd_4||D5G2;|invQ@1|vdd|P
+Evdd_5||D5G2;|invQ@1|vdd_1|P
+Evdd_6||D5G2;|invQ@1|vdd_2|P
+Evdd_7||D5G2;|invQ@1|vdd_3|P
+Evdd_8||D5G2;|invQ@2|vdd|P
+Evdd_9||D5G2;|invQ@2|vdd_1|P
+Evdd_10||D5G2;|invQ@2|vdd_2|P
+Evdd_11||D5G2;|invQ@2|vdd_3|P
+Evdd_12||D5G2;|invQ@3|vdd_2|P
+Evdd_13||D5G2;|invQ@3|vdd_3|P
+Evdd_14||D5G2;|invQ@3|vdd|P
+Evdd_15||D5G2;|invQ@3|vdd_1|P
+X