X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;ds=sidebyside;f=ships%2FLut3.ship;h=a85b8f3dd21cf438c08c81f807bf6e1dba7e2f40;hb=cbafca81451a452015ea365b3546c3bc0ac7bdbd;hp=72a51dd6b583eeee2831b9208d98d9a996401ba1;hpb=cedfa0d79cc8f11ca66d735ac58b793aa0aa72ac;p=fleet.git

diff --git a/ships/Lut3.ship b/ships/Lut3.ship
index 72a51dd..a85b8f3 100644
--- a/ships/Lut3.ship
+++ b/ships/Lut3.ship
@@ -62,44 +62,34 @@ is considered ``bit zero'').
 == FleetSim ==============================================================
 == FPGA ==============================================================
 
-  reg                    have_in1;
-  reg [(`DATAWIDTH-1):0] reg_in1;
-  reg                    have_in2;
-  reg [(`DATAWIDTH-1):0] reg_in2;
-  reg                    have_in3;
-  reg [(`DATAWIDTH-1):0] reg_in3;
-  reg                    have_inLut;
-  reg [(`DATAWIDTH-1):0] reg_inLut;
+  reg          out_draining;
+  wire [7:0]              lut;
 
-  wire [(`DATAWIDTH-1):0] out;
   genvar i;
   generate
-    for(i=0; i<`DATAWIDTH; i=i+1) begin : OUT
-      assign out[i] = reg_inLut[{reg_in3[i], reg_in2[i], reg_in1[i]}];
+    for(i=0; i<`WORDWIDTH; i=i+1) begin : OUT
+      assign out_d_[i] = lut[{in3_d[i], in2_d[i], in1_d[i]}];
     end
   endgenerate
 
+  assign lut = inLut_d[7:0];
+
   always @(posedge clk) begin
-    if (!have_in1) begin
-      `onread(in1_r, in1_a) have_in1 = 1; reg_in1 = in1_d; end
-      end else
-    if (!have_in2) begin
-      `onread(in2_r, in2_a) have_in2 = 1; reg_in2 = in2_d; end
-      end else
-    if (!have_in3) begin
-      `onread(in3_r, in3_a) have_in3 = 1; reg_in3 = in3_d; end
-      end else
-    if (!have_inLut) begin
-      `onread(inLut_r, inLut_a) have_inLut = 1; reg_inLut = inLut_d; end
-      end else
-  
-    if (have_in1 && have_in2 && have_in3 && have_inLut) begin
-      out_d = out;
-      `onwrite(out_r, out_a)
-        have_in1  = 0;
-        have_in2  = 0;
-        have_in3  = 0;
-        have_inLut = 0;
+    if (rst) begin
+      `reset
+      out_draining <= 0;
+    end else begin
+      `cleanup
+      if (out_draining && `out_empty) begin
+         `drain_in1
+         `drain_in2
+         `drain_in3
+         `drain_inLut
+         out_draining <= 0;
+      end
+      if (!out_draining && `in1_full && `in2_full && `in3_full && `inLut_full && `out_empty) begin
+         `fill_out
+         out_draining <= 1;
       end
     end
   end
@@ -365,38 +355,48 @@ is considered ``bit zero'').
 
 #ship debug        : Debug
 #ship lut          : Lut3
-#ship alu          : Alu1
+#ship alu          : Alu
 
-lut.in1:   literal 85; [*] deliver;
-lut.in2:   literal 51; [*] deliver;
-lut.in3:   literal 15; [*] deliver;
-lut.out:   [*] take, sendto debug.in;
+lut.in1:   set word= 85; set ilc=*;  deliver;
+lut.in2:   set word= 51; set ilc=*;  deliver;
+lut.in3:   set word= 15; set ilc=*;  deliver;
+lut.out:   set ilc=*;  collect, send to debug.in;
 
 // cycle through truth tables using alu as INC
+alu.in2:
+   set word= 1;
+   set ilc=*;  deliver;
 alu.inOp:
-   literal 1;
-   [120] deliver;
-   [120] deliver;
-   [15] deliver;
-alu.in:
-   literal 0;
+   set word= Alu.inOp[ADD];
+   set ilc=*;  deliver;
+alu.in1:
+   set word= 0;
    deliver;
-   [*] take, deliver;
+   set ilc=*;  recv, deliver;
 alu.out:
-  clog;
-  wait, take, sendto lut.inLut, requeue forever;
-  sendto alu.in,                requeue forever;
-  unclog;
-
-// acks from debug ship trigger new truth tables
-debug.in:
-  [*] take, deliver, notify alu.out;
+  set olc=2;
+  head;
+  recv token, collect, send to lut.inLut;
+  send to alu.in1;
+  tail;
 
 lut.inLut:
-  literal 0;
+  set word= 0;
   deliver;
-  [*] take, deliver;
+  set ilc=*;  recv, deliver;
 
+// acks from debug ship trigger new truth tables
+debug.in:
+  set ilc=63;
+  recv, deliver, send token to alu.out;
+  set ilc=63;
+  recv, deliver, send token to alu.out;
+  set ilc=63;
+  recv, deliver, send token to alu.out;
+  set ilc=63;
+  recv, deliver, send token to alu.out;
+  set ilc=4;
+  recv, deliver, send token to alu.out;