X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=Makefile;h=cd0e3d03b3185d71989ac39f3b6679f8b775d9e9;hb=9715f3f4d1708f9d5b6d3d5ae0a6beaa6b0214c3;hp=8e07843a2c7e2782b600bc95751744d83e30e359;hpb=6f0b2d4919e6db9872c2d2ff8a2696021a0a4faf;p=fleet.git

diff --git a/Makefile b/Makefile
index 8e07843..cd0e3d0 100644
--- a/Makefile
+++ b/Makefile
@@ -60,6 +60,7 @@ xilinx += PATH=$$PATH:$(remote_ise)/bin/lin:$(remote_edk)/bin/lin
 #xilinx += XST_VERSION=9.2i
 xilinx += XILINX=$(remote_ise)
 xilinx += XIL_XST_HIDEMESSAGES=hdl_and_low_levels
+xilinx += XIL_PAR_DESIGN_CHECK_VERBOSE=1
 xilinx += XILINX_EDK=$(remote_edk)
 
 xilinx_ise = $(xilinx) $(remote_ise)/bin/lin/
@@ -100,19 +101,25 @@ build/fpga/main.bit: $(java_files) $(ship_files)
 	rsync -zare ssh --progress --delete --verbose ./ ${host}:${remote_dir}
 	time ssh ${host} 'make -C ${remote_dir} synth XILINX=${remote_ise} remote_ise=${remote_ise} remote_edk=${remote_edk}'
 	scp ${host}:${remote_dir}/build/fpga/main.bit build/fpga/
+	scp ${host}:${remote_dir}/build/fpga/main.ace build/fpga/
 
 pcore = ${remote_edk}/hw/XilinxProcessorIPLib/pcores
-#effort = std
-effort = high
+intstyle = -intstyle xflow
+effort = std
+#effort = high
+opt_for = area
+#opt_for = speed
 synth:
 	cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/* .
 	cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/mem/* .
 	cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/ddr2/* .
-	#cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/greg/* .
+	cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/dvi/* .
+	cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/zbt/* .
 	rm -f build/fpga/main.lso
 	echo work                        >> build/fpga/main.lso
 	rm -f build/fpga/main.prj
 	cd build/fpga; for A in *.v;   do echo verilog work \""$$A"\"; done >> main.prj
+	cd build/fpga; for A in *.vhd; do echo vhdl    work \""$$A"\"; done >> main.prj
 	cd build/fpga; touch main.ini
 	cd build/fpga; mkdir -p tmp
 	cd build/fpga; mkdir -p xst
@@ -130,7 +137,7 @@ synth:
 	echo -n " -ofmt NGC" >> build/fpga/main.xst
 	echo -n " -p ${device}" >> build/fpga/main.xst
 	echo -n " -top main" >> build/fpga/main.xst
-	echo -n " -opt_mode area" >> build/fpga/main.xst
+	echo -n " -opt_mode ${opt_for}" >> build/fpga/main.xst
 	echo -n " -opt_level 2" >> build/fpga/main.xst
 	echo -n " -iuc NO" >> build/fpga/main.xst
 	echo -n " -lso main.lso" >> build/fpga/main.xst
@@ -200,14 +207,19 @@ synth:
 	echo '-g Security:NONE' >> build/fpga/main.ut
 	echo '-g Persist:No' >> build/fpga/main.ut
 
-	$(xilinx_ise)xst      -intstyle xflow -ifn main.xst -ofn main.syr < main.xst
-	$(xilinx_ise)ngdbuild -intstyle xflow -aul -dd _ngo -nt timestamp -uc main.ucf -p $(device) main.ngc main.ngd
-	$(xilinx_ise)map      -intstyle xflow -ol ${effort} -p $(device) -pr b -cm area -o main_map.ncd main.ngd main.pcf
-	$(xilinx_ise)par      -intstyle xflow -ol ${effort} -w main_map.ncd main.ncd main.pcf
-	$(xilinx_ise)bitgen   -intstyle xflow -f main.ut main.ncd
-#	$(xilinx_ise)trce     -intstyle xflow -e 3 -l 3 -s ${speed_grade} -xml main main.ncd -o main.twr main.pcf
-#	$(xilinx_edk)xmd -tcl $(remote_edk)/data/xmd/genace.tcl -jprog -hw main.bit -board ${board} -ace mainx.ace
-#	mv build/fpga/mainx.ace build/fpga/main.ace   # genace throws a fit if the filename prefix is the same?
+	$(xilinx_ise)xst      ${intstyle} -ifn main.xst -ofn main.syr < main.xst \
+	  | grep --line-buffered -v 'been backward balanced into' \
+	  | grep --line-buffered -v 'IDDR has been replaced by IDDR_2CLK' \
+	  | grep --line-buffered -v 'WARNING:Xst:616 - Invalid property'
+	#rm build/fpga/dvi.ucf
+	cat build/fpga/*.ucf > build/fpga/main.ucf
+	$(xilinx_ise)ngdbuild ${intstyle} -aul -dd _ngo -nt timestamp -uc main.ucf -p $(device) main.ngc main.ngd
+	$(xilinx_ise)map      ${intstyle} -ol ${effort} -p $(device) -pr b -cm ${opt_for} -o main_map.ncd main.ngd main.pcf
+	$(xilinx_ise)par      ${intstyle} -pl ${effort} -ol ${effort} -w main_map.ncd main.ncd main.pcf
+	$(xilinx_ise)trce     ${intstyle} -e 3 -l 3 -s ${speed_grade} -xml main main.ncd -o main.twr main.pcf
+	$(xilinx_ise)bitgen   ${intstyle} -f main.ut main.ncd
+	$(xilinx) tcl $(remote_edk)/data/xmd/genace.tcl -jprog -hw main.bit -board ${board} -ace mainx.ace
+	mv build/fpga/mainx.ace build/fpga/main.ace   # genace throws a fit if the filename prefix is the same?
 
 
 runserver: fleet.jar
@@ -342,14 +354,14 @@ sun_server = frehley
 
 runtest: fleet.jar
 	rm lib/suncvs.jar; make lib/suncvs.jar
-	rm -f suncvs/marina/testSims/isolatedInDock.spi.run
+	cp lib/suncvs.jar suncvs/marina/testCode/MarinaTest.jar
 	ssh ${sun_server} 'skill nanosim'
 	rsync -are ssh --delete --progress --verbose ./ ${sun_server}:~/fleet/
-	ssh ${sun_server} 'export PATH=$$PATH:/proj/async/cad/linux/bin/; cd ~/fleet/suncvs/marina/testSims; ln -s ../testCode/marina.xml ../testCode/marina.spi ../testCode/cfg .; /proj/async/cad/linux/lib/jdk1.5.0_05-linux-i586/bin/java  -cp $$HOME/fleet/fleet.jar:$$HOME/fleet/lib/suncvs.jar com.sun.vlsi.chips.marina.test.MarinaTest -testNum 3021'
+	ssh -Y ${sun_server} 'export PATH=/proj/async/cad/linux/bin/:$$PATH; cd ~/fleet/suncvs/marina/testCode; /proj/async/cad/linux/lib/jdk1.5.0_05-linux-i586/bin/java -cp $$HOME/fleet/lib/suncvs.jar com.sun.vlsi.chips.marina.test.MarinaTest -testNum 3'
 
 electric:
 	rsync -are ssh --progress --verbose ${sun_server}:fleet/suncvs/marina/testSims/marina.spi.out ~/marina.spi.out
-	java -Xmx900m -jar /Applications/electric.jar suncvs/marina/electric/marinaL.jelib
+	java -Xmx900m -jar /Applications/electric.jar suncvs/marina/electric/aMarinaM.jelib
 
 suncvs/test:
 	mkdir -p suncvs
@@ -359,6 +371,8 @@ suncvs/marina:
 	mkdir -p suncvs
 	cd suncvs; cvs -d ${sun_server}:/import/async/cad/cvs co marina
 
+chaing: lib/suncvs.jar
+	java -cp lib/suncvs.jar com.sun.async.test.ChainG suncvs/marina/testCode/marina.xml
 
 syncspi:
-	rsync -are ssh --progress --verbose frehley:fleet/suncvs/marina/testSims/marina.spi.out ~/marina.spi.out
+	rsync -are ssh --progress --verbose frehley:fleet/suncvs/marina/testCode/marina.spi.out ~/marina.spi.out