X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=bee2-selectmap%2F.svn%2Ftext-base%2FMakefile.svn-base;fp=bee2-selectmap%2F.svn%2Ftext-base%2FMakefile.svn-base;h=a6e171790e25eb04500a47844720f2687ebdcd01;hb=3d1e9b6ed214e780d02cb7693423c0d1ecb0cfc6;hp=0000000000000000000000000000000000000000;hpb=7e45bc4adf44a4dd870cbadb466de8413f282d6e;p=fleet.git

diff --git a/bee2-selectmap/.svn/text-base/Makefile.svn-base b/bee2-selectmap/.svn/text-base/Makefile.svn-base
new file mode 100644
index 0000000..a6e1717
--- /dev/null
+++ b/bee2-selectmap/.svn/text-base/Makefile.svn-base
@@ -0,0 +1,52 @@
+
+projectname = bee2-control-user-fifo
+
+build_machine = sting.eecs.berkeley.edu
+build_machine_xilinx_path = /opt/xilinx/ISE9.2i_lin/
+build_machine_work_dir = ~/$(projectname)
+bee2_machine = bee441.megacz.com
+
+## you probably want to customize the stuff above this line
+
+## you probably don't want to change anything below this line
+
+xilinx =  cd $(build_machine_work_dir);
+xilinx += LD_LIBRARY_PATH=$$LD_LIBRARY_PATH:$(XILINX)/bin/lin
+xilinx += XILINX=$(XILINX)
+xilinx += PATH=$$PATH:$(XILINX)/bin/lin
+xilinx += $(XILINX)/bin/lin/
+
+bitfile = bee2-control-user-fifo.bit
+
+remote_run  = user_unprogram 1;
+remote_run += user_program 1 $(bitfile);
+remote_run += echo "Gdkkn+vnqkc " > /dev/selectmap1;
+remote_run += head -c12 /dev/selectmap1; echo
+
+verilog_files = $(find . -name \*.v)
+
+run: upload build/fpga/$(bitfile)
+	ssh root@$(bee2_machine) '$(remote_run)'
+
+upload: build/fpga/$(bitfile)
+	rsync -zare ssh --progress --verbose build/fpga/$(bitfile) root@$(bee2_machine):
+
+build/fpga/$(bitfile): $(verilog_files)
+	mkdir -p build/fpga/
+	rsync -zare ssh --progress --delete --verbose ./ ${build_machine}:${build_machine_work_dir}
+	time ssh ${build_machine} 'make -C ${build_machine_work_dir} synth XILINX=${build_machine_xilinx_path}'
+	scp ${build_machine}:${build_machine_work_dir}/main.bit build/fpga/$(bitfile)
+
+synth:
+	mkdir -p build/fpga/
+	echo work > main.lso
+	for A in *.v; do echo verilog work \""$$A"\"; done > main.prj
+	mkdir -p tmp
+	mkdir -p xst
+	rm -rf build/fpga/_ngo
+	$(xilinx)xst -intstyle xflow -ifn main.xst -ofn main.syr < main.xst
+	$(xilinx)ngdbuild -intstyle xflow -dd _ngo -nt timestamp -uc main.ucf -p xc2vp70-ff1704-6 main.ngc main.ngd
+	$(xilinx)map -intstyle xflow -p xc2vp70-ff1704-6 -cm speed -l -pr b -k 4 -c 100 -tx off -o main_map.ncd main.ngd main.pcf
+	$(xilinx)par -w -intstyle xflow -pl std -ol std -t 99 main_map.ncd main.ncd main.pcf
+	$(xilinx)bitgen -intstyle xflow -d -f main.ut main.ncd
+#	$(xilinx)trce -intstyle xflow -e 3 -l 3 -s 6 -xml main main.ncd -o main.twr main.pcf