X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=compiler%2FnativeGen%2FMachCodeGen.hs;fp=compiler%2FnativeGen%2FMachCodeGen.hs;h=002adf9a5e2b10ebc4f60b8fd77b3a1d6f33642d;hb=bddb8ebe61ae38c4f4eb766966cf1caee7fb1de2;hp=1cfc7a3eff722ee436ae5b32263100ed359884ac;hpb=c0ea29afb7fcc3e8a69df60704d170d2c45e3d90;p=ghc-hetmet.git

diff --git a/compiler/nativeGen/MachCodeGen.hs b/compiler/nativeGen/MachCodeGen.hs
index 1cfc7a3..002adf9 100644
--- a/compiler/nativeGen/MachCodeGen.hs
+++ b/compiler/nativeGen/MachCodeGen.hs
@@ -3616,6 +3616,16 @@ genCCall
 
 -}
 
+
+-- On SPARC under TSO (Total Store Ordering), writes earlier in the instruction stream
+-- are guaranteed to take place before writes afterwards (unlike on PowerPC). 
+-- Ref: Section 8.4 of the SPARC V9 Architecture manual.
+--
+-- In the SPARC case we don't need a barrier.
+--
+genCCall (CmmPrim (MO_WriteBarrier)) _ _
+ = do	return nilOL
+
 genCCall target dest_regs argsAndHints 
  = do	 	
 	-- strip hints from the arg regs