X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=compiler%2FnativeGen%2FMachCodeGen.hs;h=5f973ef1b609e613b7d20ab98b8573b728e3522b;hb=2984649a87ffad1753be0c950ed18cfc40f55fea;hp=d9b2028a304429e251e1379d21d656d3b62ea2d9;hpb=87b5b19f2166dab386aab7d58aae9bb25264b92b;p=ghc-hetmet.git

diff --git a/compiler/nativeGen/MachCodeGen.hs b/compiler/nativeGen/MachCodeGen.hs
index d9b2028..5f973ef 100644
--- a/compiler/nativeGen/MachCodeGen.hs
+++ b/compiler/nativeGen/MachCodeGen.hs
@@ -371,6 +371,26 @@ iselExpr64 (CmmMachOp (MO_Add _) [e1, CmmLit (CmmInt i _)])
 			r_dst_lo
 
 
+-- Addition of II64
+iselExpr64 (CmmMachOp (MO_Add width) [e1, e2])
+ = do	ChildCode64 code1 r1_lo	<- iselExpr64 e1
+	let r1_hi	= getHiVRegFromLo r1_lo
+
+ 	ChildCode64 code2 r2_lo	<- iselExpr64 e2
+	let r2_hi	= getHiVRegFromLo r2_lo
+	
+	r_dst_lo	<- getNewRegNat II32
+	let r_dst_hi	= getHiVRegFromLo r_dst_lo
+	
+	let code =	code1
+		`appOL`	code2
+		`appOL`	toOL
+			[ ADD False False r1_lo (RIReg r2_lo) r_dst_lo
+			, ADD True  False r1_hi (RIReg r2_hi) r_dst_hi ]
+	
+	return	$ ChildCode64 code r_dst_lo
+
+
 iselExpr64 (CmmReg (CmmLocal (LocalReg uq ty))) | isWord64 ty = do
      r_dst_lo <-  getNewRegNat II32
      let r_dst_hi = getHiVRegFromLo r_dst_lo
@@ -383,6 +403,23 @@ iselExpr64 (CmmReg (CmmLocal (LocalReg uq ty))) | isWord64 ty = do
             ChildCode64 (toOL [mov_hi, mov_lo]) r_dst_lo
          )
 
+-- Convert something into II64
+iselExpr64 (CmmMachOp (MO_UU_Conv _ W64) [expr]) 
+ = do
+	r_dst_lo 	<- getNewRegNat II32
+	let r_dst_hi	= getHiVRegFromLo r_dst_lo
+
+	-- compute expr and load it into r_dst_lo
+	(a_reg, a_code)	<- getSomeReg expr
+
+	let code	= a_code
+		`appOL`	toOL
+			[ mkRegRegMoveInstr g0    r_dst_hi 	-- clear high 32 bits
+			, mkRegRegMoveInstr a_reg r_dst_lo ]
+			
+	return	$ ChildCode64 code r_dst_lo
+
+
 iselExpr64 expr
    = pprPanic "iselExpr64(sparc)" (ppr expr)
 
@@ -3567,8 +3604,9 @@ genCCall target dest_regs args = do
 	 (arg_op, arg_code) <- getOperand arg
          delta <- getDeltaNat
          setDeltaNat (delta-arg_size)
-	 let code' = code `appOL` toOL [PUSH II64 arg_op, 
-	 			        DELTA (delta-arg_size)]
+	 let code' = code `appOL` arg_code `appOL` toOL [
+                        PUSH II64 arg_op, 
+	 		DELTA (delta-arg_size)]
 	 push_args rest code'
 	where
 	  arg_rep = cmmExprType arg
@@ -3615,6 +3653,16 @@ genCCall
 
 -}
 
+
+-- On SPARC under TSO (Total Store Ordering), writes earlier in the instruction stream
+-- are guaranteed to take place before writes afterwards (unlike on PowerPC). 
+-- Ref: Section 8.4 of the SPARC V9 Architecture manual.
+--
+-- In the SPARC case we don't need a barrier.
+--
+genCCall (CmmPrim (MO_WriteBarrier)) _ _
+ = do	return nilOL
+
 genCCall target dest_regs argsAndHints 
  = do	 	
 	-- strip hints from the arg regs
@@ -3815,6 +3863,7 @@ outOfLineFloatOp_table mop
 	MO_F32_Exp    -> fsLit "expf"
 	MO_F32_Log    -> fsLit "logf"
 	MO_F32_Sqrt   -> fsLit "sqrtf"
+	MO_F32_Pwr    -> fsLit "powf"
 
 	MO_F32_Sin    -> fsLit "sinf"
 	MO_F32_Cos    -> fsLit "cosf"
@@ -3831,6 +3880,7 @@ outOfLineFloatOp_table mop
 	MO_F64_Exp    -> fsLit "exp"
 	MO_F64_Log    -> fsLit "log"
 	MO_F64_Sqrt   -> fsLit "sqrt"
+	MO_F64_Pwr    -> fsLit "pow"
 
 	MO_F64_Sin    -> fsLit "sin"
 	MO_F64_Cos    -> fsLit "cos"
@@ -4261,8 +4311,8 @@ genSwitch expr ids
 			, SLL   e_reg (RIImm $ ImmInt 2) offset_reg
 
 			-- load and jump to the destination
-			, LD 	II32 (AddrRegReg base_reg offset_reg) dst
-			, JMP   (AddrRegImm dst (ImmInt 0)) 
+			, LD 	  II32 (AddrRegReg base_reg offset_reg) dst
+			, JMP_TBL (AddrRegImm dst (ImmInt 0)) [i | Just i <- ids]
 			, NOP ]
 
 #else