X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=compiler%2FnativeGen%2FMachInstrs.hs;h=6316d94265f01ff8fea516869d55b2be756c0304;hb=923ee9d360ed15331ac6faf8a6b4aca334fc0cee;hp=0f718d3ceacda83eb0f5c37ad133444084b0a505;hpb=0065d5ab628975892cea1ec7303f968c3338cbe1;p=ghc-hetmet.git

diff --git a/compiler/nativeGen/MachInstrs.hs b/compiler/nativeGen/MachInstrs.hs
index 0f718d3..6316d94 100644
--- a/compiler/nativeGen/MachInstrs.hs
+++ b/compiler/nativeGen/MachInstrs.hs
@@ -15,7 +15,9 @@ module MachInstrs (
 	-- * Machine instructions
 	Instr(..),
 	Cond(..), condUnsigned, condToSigned, condToUnsigned,
-
+#if powerpc_TARGET_ARCH
+        condNegate,
+#endif
 #if !powerpc_TARGET_ARCH && !i386_TARGET_ARCH && !x86_64_TARGET_ARCH
 	Size(..), machRepSize,
 #endif
@@ -43,7 +45,7 @@ import Outputable
 import FastString
 import Constants       ( wORD_SIZE )
 
-import GLAEXTS
+import GHC.Exts
 
 
 -- -----------------------------------------------------------------------------
@@ -140,6 +142,20 @@ condToUnsigned GE  = GEU
 condToUnsigned LE  = LEU
 condToUnsigned x   = x
 
+#if powerpc_TARGET_ARCH
+condNegate ALWAYS  = panic "condNegate: ALWAYS"
+condNegate EQQ     = NE
+condNegate GE      = LTT
+condNegate GEU     = LU
+condNegate GTT     = LE
+condNegate GU      = LEU
+condNegate LE      = GTT
+condNegate LEU     = GU
+condNegate LTT     = GE
+condNegate LU      = GEU
+condNegate NE      = EQQ
+#endif
+
 -- -----------------------------------------------------------------------------
 -- Sizes on this architecture
 
@@ -472,8 +488,8 @@ bit or 64 bit precision.
 
 	| CVTSS2SD	Reg Reg		-- F32 to F64
 	| CVTSD2SS	Reg Reg		-- F64 to F32
-	| CVTSS2SI	Operand Reg	-- F32 to I32/I64 (with rounding)
-	| CVTSD2SI	Operand	Reg	-- F64 to I32/I64 (with rounding)
+	| CVTTSS2SIQ	Operand Reg	-- F32 to I32/I64 (with truncation)
+	| CVTTSD2SIQ	Operand	Reg	-- F64 to I32/I64 (with truncation)
 	| CVTSI2SS	Operand Reg	-- I32/I64 to F32
 	| CVTSI2SD	Operand Reg	-- I32/I64 to F64
 
@@ -504,6 +520,7 @@ bit or 64 bit precision.
 -- Jumping around.
 	| JMP	      Operand
 	| JXX	      Cond BlockId  -- includes unconditional branches
+	| JXX_GBL     Cond Imm      -- non-local version of JXX
 	| JMP_TBL     Operand [BlockId]  -- table jump
 	| CALL	      (Either Imm Reg) [Reg]
 
@@ -660,6 +677,7 @@ fPair other = pprPanic "fPair(sparc NCG)" (ppr other)
 	      | CMPL    MachRep Reg RI --- size, src1, src2
 	      
 	      | BCC     Cond BlockId
+	      | BCCFAR  Cond BlockId
               | JMP     CLabel          -- same as branch,
                                         -- but with CLabel instead of block ID
 	      | MTCTR	Reg
@@ -719,4 +737,5 @@ fPair other = pprPanic "fPair(sparc NCG)" (ppr other)
 	      | FETCHPC Reg            -- pseudo-instruction:
 	                               -- bcl to next insn, mflr reg
 	      
+	      | LWSYNC -- memory barrier
 #endif /* powerpc_TARGET_ARCH */