X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=compiler%2FnativeGen%2FMachInstrs.hs;h=a0bf9ac973ae190567afd8a8690dfae13a5f040b;hb=72db4d050b1f9d9058d1427eaad9833be03a5537;hp=96db72dcad78101348996abd8d9642b37d7eeb2a;hpb=22bbcd1dcd94851b8f9409310cf95f3b9332850c;p=ghc-hetmet.git

diff --git a/compiler/nativeGen/MachInstrs.hs b/compiler/nativeGen/MachInstrs.hs
index 96db72d..a0bf9ac 100644
--- a/compiler/nativeGen/MachInstrs.hs
+++ b/compiler/nativeGen/MachInstrs.hs
@@ -6,6 +6,13 @@
 --
 -----------------------------------------------------------------------------
 
+{-# OPTIONS -w #-}
+-- The above warning supression flag is a temporary kludge.
+-- While working on this module you are encouraged to remove it and fix
+-- any warnings in the module. See
+--     http://hackage.haskell.org/trac/ghc/wiki/Commentary/CodingStyle#Warnings
+-- for details
+
 #include "nativeGen/NCG.h"
 
 module MachInstrs (
@@ -52,8 +59,8 @@ import GHC.Exts
 -- Our flavours of the Cmm types
 
 -- Type synonyms for Cmm populated with native code
-type NatCmm        = GenCmm CmmStatic Instr
-type NatCmmTop     = GenCmmTop CmmStatic Instr
+type NatCmm        = GenCmm CmmStatic [CmmStatic] (ListGraph Instr)
+type NatCmmTop     = GenCmmTop CmmStatic [CmmStatic] (ListGraph Instr)
 type NatBasicBlock = GenBasicBlock Instr
 
 -- -----------------------------------------------------------------------------
@@ -226,6 +233,9 @@ data Instr
   | DELTA   Int                 -- specify current stack offset for
                                 -- benefit of subsequent passes
 
+  | SPILL   Reg Int		-- ^ spill this reg to a stack slot
+  | RELOAD  Int Reg		-- ^ reload this reg from a stack slot
+
 -- -----------------------------------------------------------------------------
 -- Alpha instructions
 
@@ -488,8 +498,8 @@ bit or 64 bit precision.
 
 	| CVTSS2SD	Reg Reg		-- F32 to F64
 	| CVTSD2SS	Reg Reg		-- F64 to F32
-	| CVTSS2SI	Operand Reg	-- F32 to I32/I64 (with rounding)
-	| CVTSD2SI	Operand	Reg	-- F64 to I32/I64 (with rounding)
+	| CVTTSS2SIQ	Operand Reg	-- F32 to I32/I64 (with truncation)
+	| CVTTSD2SIQ	Operand	Reg	-- F64 to I32/I64 (with truncation)
 	| CVTSI2SS	Operand Reg	-- I32/I64 to F32
 	| CVTSI2SD	Operand Reg	-- I32/I64 to F64