X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=compiler%2FnativeGen%2FMachRegs.lhs;h=2c6238d83442b162cba7c9903aac7050233a58c4;hb=3629180909c5ffcc9056b8fca262021021dbfab6;hp=522f7153c4015384a551903d4a9694cf1729a880;hpb=983c316af4654b6532909a0e85dec175e808401a;p=ghc-hetmet.git

diff --git a/compiler/nativeGen/MachRegs.lhs b/compiler/nativeGen/MachRegs.lhs
index 522f715..2c6238d 100644
--- a/compiler/nativeGen/MachRegs.lhs
+++ b/compiler/nativeGen/MachRegs.lhs
@@ -103,10 +103,10 @@ import qualified Outputable
 import Unique
 import UniqSet
 import Constants
+import FastTypes
 import FastBool
-import UniqFM
-
-import GHC.Exts
+import qualified UniqFM as S
+import LazyUniqFM
 
 #if powerpc_TARGET_ARCH
 import Data.Word	( Word8, Word16, Word32 )
@@ -503,49 +503,50 @@ worst n classN classC
 -- Compare MachRegs.freeRegs  and MachRegs.h to get these numbers.
 --
 #if i386_TARGET_ARCH
-#define ALLOCATABLE_REGS_INTEGER 3#
-#define ALLOCATABLE_REGS_DOUBLE  6#
-#endif
+#define ALLOCATABLE_REGS_INTEGER (_ILIT(3))
+#define ALLOCATABLE_REGS_DOUBLE  (_ILIT(6))
 
-#if x86_64_TARGET_ARCH
-#define ALLOCATABLE_REGS_INTEGER 5#
-#define ALLOCATABLE_REGS_DOUBLE  2#
-#endif
+#elif x86_64_TARGET_ARCH
+#define ALLOCATABLE_REGS_INTEGER (_ILIT(5))
+#define ALLOCATABLE_REGS_DOUBLE  (_ILIT(2))
 
-#if powerpc_TARGET_ARCH
-#define ALLOCATABLE_REGS_INTEGER 16#
-#define ALLOCATABLE_REGS_DOUBLE  26#
+#elif powerpc_TARGET_ARCH
+#define ALLOCATABLE_REGS_INTEGER (_ILIT(16))
+#define ALLOCATABLE_REGS_DOUBLE  (_ILIT(26))
+
+#else
+#error ToDo: define ALLOCATABLE_REGS_INTEGER and ALLOCATABLE_REGS_DOUBLE
 #endif
 
 {-# INLINE regClass      #-}
 trivColorable :: RegClass -> UniqSet Reg -> UniqSet Reg -> Bool
-trivColorable classN conflicts exclusions
+trivColorable classN (MkUniqFM conflicts) (MkUniqFM exclusions)
  = {-# SCC "trivColorable" #-}
    let
 	{-# INLINE   isSqueesed    #-}
 	isSqueesed cI cF ufm
 	  = case ufm of
-		NodeUFM _ _ left right
+		S.NodeUFM _ _ left right
 		 -> case isSqueesed cI cF right of
 		 	(# s, cI', cF' #)
 			 -> case s of
 			 	False	-> isSqueesed cI' cF' left
 				True	-> (# True, cI', cF' #)
 
-		LeafUFM _ reg
+		S.LeafUFM _ (Lazy reg)
 		 -> case regClass reg of
 		 	RcInteger
-			 -> case cI +# 1# of
+			 -> case cI +# _ILIT(1) of
 			  	cI' -> (# cI' >=# ALLOCATABLE_REGS_INTEGER, cI', cF #)
 
 			RcDouble
-			 -> case cF +# 1# of
+			 -> case cF +# _ILIT(1) of
 			 	cF' -> (# cF' >=# ALLOCATABLE_REGS_DOUBLE,  cI, cF' #)
 
-		EmptyUFM
+		S.EmptyUFM
 		 ->	(# False, cI, cF #)
 
-   in case isSqueesed 0# 0# conflicts of
+   in case isSqueesed (_ILIT(0)) (_ILIT(0)) conflicts of
 	(# False, cI', cF' #)
 	 -> case isSqueesed cI' cF' exclusions of
 		(# s, _, _ #)	-> not s