X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=compiler%2FnativeGen%2FMachRegs.lhs;h=b4af0463ad62058ebd2518d88afa37369530c36d;hb=598d761c769316dc4550028285f6508538b8a99c;hp=5267e5bae38265ee9b5d17b1e64bdaa87cfd3648;hpb=e6243a818496aad82b6f47511d3bd9bc800f747d;p=ghc-hetmet.git

diff --git a/compiler/nativeGen/MachRegs.lhs b/compiler/nativeGen/MachRegs.lhs
index 5267e5b..b4af046 100644
--- a/compiler/nativeGen/MachRegs.lhs
+++ b/compiler/nativeGen/MachRegs.lhs
@@ -74,7 +74,7 @@ module MachRegs (
 	addrModeRegs, allFPArgRegs,
 #endif
 #if sparc_TARGET_ARCH
-	fits13Bits,
+	fits13Bits, 
 	fpRel, gReg, iReg, lReg, oReg, largeOffsetError,
 	fp, sp, g0, g1, g2, o0, o1, f0, f6, f8, f26, f27,
 #endif
@@ -194,14 +194,53 @@ data Size
 
 #if sparc_TARGET_ARCH /* || powerpc_TARGET_ARCH */
 data Size
-    = B     -- byte (signed)
-    | Bu    -- byte (unsigned)
-    | H     -- halfword (signed, 2 bytes)
-    | Hu    -- halfword (unsigned, 2 bytes)
-    | W	    -- word (4 bytes)
-    | F	    -- IEEE single-precision floating pt
-    | DF    -- IEEE single-precision floating pt
+    = II8     -- byte (signed)
+    | II8u    -- byte (unsigned)
+    | II16    -- halfword (signed, 2 bytes)
+    | II16u   -- halfword (unsigned, 2 bytes)
+    | II32    -- word (4 bytes)
+    | II64    -- word (8 bytes)
+    | FF32    -- IEEE single-precision floating pt
+    | FF64    -- IEEE single-precision floating pt
   deriving Eq
+
+
+intSize, floatSize :: Width -> Size
+intSize W8  = II8
+intSize W16 = II16u
+intSize W32 = II32
+intSize W64 = II64
+intSize other = pprPanic "MachInstrs.intSize" (ppr other)
+
+floatSize W32 = FF32
+floatSize W64 = FF64
+floatSize other = pprPanic "MachInstrs.intSize" (ppr other)
+
+wordSize :: Size
+wordSize = intSize wordWidth
+
+isFloatSize :: Size -> Bool
+isFloatSize FF32	= True
+isFloatSize FF64	= True
+isFloatSize _		= False
+
+cmmTypeSize :: CmmType -> Size
+cmmTypeSize ty | isFloatType ty = floatSize (typeWidth ty)
+	       | otherwise	= intSize (typeWidth ty)
+
+sizeToWidth :: Size -> Width
+sizeToWidth size
+ = case size of
+ 	II8		-> W8
+	II8u		-> W8
+	II16		-> W16
+	II16u		-> W16
+	II32		-> W32
+	II64		-> W64
+	FF32		-> W32
+	FF64		-> W64
+
+
 #endif
 
 -- -----------------------------------------------------------------------------
@@ -229,7 +268,10 @@ data Imm
 strImmLit s = ImmLit (text s)
 
 litToImm :: CmmLit -> Imm
-litToImm (CmmInt i _)        = ImmInteger i
+litToImm (CmmInt i w)        = ImmInteger (narrowS w i)
+                -- narrow to the width: a CmmInt might be out of
+                -- range, but we assume that ImmInteger only contains
+                -- in-range values.  A signed value should be fine here.
 litToImm (CmmFloat f W32)    = ImmFloat f
 litToImm (CmmFloat f W64)    = ImmDouble f
 litToImm (CmmLabel l)        = ImmCLbl l
@@ -491,10 +533,11 @@ mkVReg u size
    = case size of
 #if sparc_TARGET_ARCH
         FF32    -> VirtualRegF u
+	FF64	-> VirtualRegD u
 #else
         FF32    -> VirtualRegD u
-#endif
         FF64    -> VirtualRegD u
+#endif
 	_other -> panic "mkVReg"
 
 isVirtualReg :: Reg -> Bool
@@ -607,6 +650,10 @@ worst n classN classC
 #define ALLOCATABLE_REGS_INTEGER (_ILIT(16))
 #define ALLOCATABLE_REGS_DOUBLE  (_ILIT(26))
 
+#elif sparc_TARGET_ARCH
+#define ALLOCATABLE_REGS_INTEGER (_ILIT(3))
+#define ALLOCATABLE_REGS_DOUBLE  (_ILIT(6))
+
 #else
 #error ToDo: define ALLOCATABLE_REGS_INTEGER and ALLOCATABLE_REGS_DOUBLE
 #endif
@@ -616,7 +663,6 @@ trivColorable :: RegClass -> UniqSet Reg -> UniqSet Reg -> Bool
 trivColorable classN conflicts exclusions
  = {-# SCC "trivColorable" #-}
    let
-	{-# INLINE   isSqueesed    #-}
 	isSqueesed cI cF ufm
 	  = case ufm of
 		NodeUFM _ _ left right