X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=compiler%2FnativeGen%2FReg.hs;h=50d179c00252fc5bd17eefd2572558ceb05360c0;hb=9a82b1ffa35fa4c3927c66a1037a37d436cf6aac;hp=1da72c4cefffea7f10aeb4a9887b6730dab8b358;hpb=703ca1542c8e0983cc9d8eebce6e9f3dd3fd71e2;p=ghc-hetmet.git

diff --git a/compiler/nativeGen/Reg.hs b/compiler/nativeGen/Reg.hs
index 1da72c4..50d179c 100644
--- a/compiler/nativeGen/Reg.hs
+++ b/compiler/nativeGen/Reg.hs
@@ -55,6 +55,7 @@ data VirtualReg
 	| VirtualRegHi {-# UNPACK #-} !Unique  -- High part of 2-word register
 	| VirtualRegF  {-# UNPACK #-} !Unique
 	| VirtualRegD  {-# UNPACK #-} !Unique
+	| VirtualRegSSE {-# UNPACK #-} !Unique
 	deriving (Eq, Show, Ord)
 
 instance Uniquable VirtualReg where
@@ -64,6 +65,7 @@ instance Uniquable VirtualReg where
 		VirtualRegHi u	-> u
 		VirtualRegF u	-> u
 		VirtualRegD u	-> u
+		VirtualRegSSE u	-> u
 
 instance Outputable VirtualReg where
 	ppr reg
@@ -72,6 +74,7 @@ instance Outputable VirtualReg where
 		VirtualRegHi u  -> text "%vHi_" <> pprUnique u
 		VirtualRegF  u  -> text "%vF_" 	<> pprUnique u
 		VirtualRegD  u  -> text "%vD_" 	<> pprUnique u
+		VirtualRegSSE u -> text "%vSSE_" <> pprUnique u
 
 
 renameVirtualReg :: Unique -> VirtualReg -> VirtualReg
@@ -81,6 +84,7 @@ renameVirtualReg u r
 	VirtualRegHi _	-> VirtualRegHi u
 	VirtualRegF _	-> VirtualRegF  u
 	VirtualRegD _	-> VirtualRegD  u
+	VirtualRegSSE _	-> VirtualRegSSE u
 
 
 classOfVirtualReg :: VirtualReg -> RegClass
@@ -90,6 +94,7 @@ classOfVirtualReg vr
 	VirtualRegHi{}	-> RcInteger
 	VirtualRegF{}	-> RcFloat
 	VirtualRegD{}	-> RcDouble
+	VirtualRegSSE{}	-> RcDoubleSSE
 
 
 -- Determine the upper-half vreg for a 64-bit quantity on a 32-bit platform
@@ -125,8 +130,8 @@ data RealReg
 instance Uniquable RealReg where
 	getUnique reg
 	 = case reg of
-	 	RealRegSingle i		-> mkUnique 'S' i
-		RealRegPair r1 r2	-> mkUnique 'P' (r1 * 65536 + r2)
+	 	RealRegSingle i		-> mkRegSingleUnique i
+		RealRegPair r1 r2	-> mkRegPairUnique (r1 * 65536 + r2)
 
 instance Outputable RealReg where
 	ppr reg
@@ -148,8 +153,8 @@ realRegsAlias rr1 rr2
 --------------------------------------------------------------------------------
 -- | A register, either virtual or real
 data Reg
-	= RegVirtual {-# UNPACK #-} !VirtualReg
-	| RegReal    {-# UNPACK #-} !RealReg
+	= RegVirtual !VirtualReg
+	| RegReal    !RealReg
 	deriving (Eq, Ord)
 
 regSingle :: RegNo -> Reg