X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=compiler%2FnativeGen%2FRegAlloc%2FLinear%2FBase.hs;h=432acdf314111f7e741d54defce020049cd96459;hb=HEAD;hp=087ab9c8156d0d49ed7f4cd747c82f798575144e;hpb=6fe4f8d560bedfd21289a1a9f9360a371b3a5246;p=ghc-hetmet.git

diff --git a/compiler/nativeGen/RegAlloc/Linear/Base.hs b/compiler/nativeGen/RegAlloc/Linear/Base.hs
index 087ab9c..432acdf 100644
--- a/compiler/nativeGen/RegAlloc/Linear/Base.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/Base.hs
@@ -18,7 +18,6 @@ module RegAlloc.Linear.Base (
 
 where
 
-import RegAlloc.Linear.FreeRegs
 import RegAlloc.Linear.StackMap
 import RegAlloc.Liveness
 import Reg
@@ -34,8 +33,8 @@ import UniqSupply
 --      target a particular label. We have to insert fixup code to make
 --      the register assignments from the different sources match up.
 --
-type BlockAssignment
-        = BlockMap (FreeRegs, RegMap Loc)
+type BlockAssignment freeRegs
+        = BlockMap (freeRegs, RegMap Loc)
 
 
 -- | Where a vreg is currently stored
@@ -101,16 +100,16 @@ data RegAllocStats
 
 
 -- | The register alloctor state
-data RA_State
+data RA_State freeRegs
         = RA_State
 
         {
         -- | the current mapping from basic blocks to
         --      the register assignments at the beginning of that block.
-          ra_blockassig :: BlockAssignment
+          ra_blockassig :: BlockAssignment freeRegs
 
         -- | free machine registers
-        , ra_freeregs   :: {-#UNPACK#-}!FreeRegs
+        , ra_freeregs   :: !freeRegs
 
         -- | assignment of temps to locations
         , ra_assig      :: RegMap Loc
@@ -131,7 +130,7 @@ data RA_State
 
 
 -- | The register allocator monad type.
-newtype RegM a
-        = RegM { unReg :: RA_State -> (# RA_State, a #) }
+newtype RegM freeRegs a
+        = RegM { unReg :: RA_State freeRegs -> (# RA_State freeRegs, a #) }