X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=compiler%2FnativeGen%2FRegAlloc%2FLinear%2FX86%2FFreeRegs.hs;h=0a15e5682c5d97674afc3cb5d0dea10306762c73;hb=3fd25ca4ae2b41c283210112c6e710e8a44804ba;hp=1306deb15998b42b6e1499bd75bb881c4caab856;hpb=a12e845684c10955bc594cdb20d1f13fae14873d;p=ghc-hetmet.git

diff --git a/compiler/nativeGen/RegAlloc/Linear/X86/FreeRegs.hs b/compiler/nativeGen/RegAlloc/Linear/X86/FreeRegs.hs
index 1306deb..0a15e56 100644
--- a/compiler/nativeGen/RegAlloc/Linear/X86/FreeRegs.hs
+++ b/compiler/nativeGen/RegAlloc/Linear/X86/FreeRegs.hs
@@ -3,38 +3,53 @@
 module RegAlloc.Linear.X86.FreeRegs
 where
 
-import Regs
+import X86.Regs
+import RegClass
+import Reg
+import Panic
 
 import Data.Word
 import Data.Bits
-import Data.List
 
 type FreeRegs 
+#ifdef i386_TARGET_ARCH
 	= Word32
+#else
+	= Word64
+#endif
 
 noFreeRegs :: FreeRegs
 noFreeRegs = 0
 
-releaseReg :: RegNo -> FreeRegs -> FreeRegs
-releaseReg n f = f .|. (1 `shiftL` n)
+releaseReg :: RealReg -> FreeRegs -> FreeRegs
+releaseReg (RealRegSingle n) f 
+	= f .|. (1 `shiftL` n)
+
+releaseReg _ _	
+	= panic "RegAlloc.Linear.X86.FreeRegs.realeaseReg: no reg"
 
 initFreeRegs :: FreeRegs
-initFreeRegs = foldr releaseReg noFreeRegs allocatableRegs
+initFreeRegs 
+	= foldr releaseReg noFreeRegs allocatableRegs
 
-getFreeRegs :: RegClass -> FreeRegs -> [RegNo]	-- lazilly
+getFreeRegs :: RegClass -> FreeRegs -> [RealReg]	-- lazilly
 getFreeRegs cls f = go f 0
 
   where go 0 _ = []
         go n m 
-	  | n .&. 1 /= 0 && regClass (RealReg m) == cls
-	  = m : (go (n `shiftR` 1) $! (m+1))
+	  | n .&. 1 /= 0 && classOfRealReg (RealRegSingle m) == cls
+	  = RealRegSingle m : (go (n `shiftR` 1) $! (m+1))
 
 	  | otherwise
 	  = go (n `shiftR` 1) $! (m+1)
 	-- ToDo: there's no point looking through all the integer registers
 	-- in order to find a floating-point one.
 
-allocateReg :: RegNo -> FreeRegs -> FreeRegs
-allocateReg r f = f .&. complement (1 `shiftL` fromIntegral r)
+allocateReg :: RealReg -> FreeRegs -> FreeRegs
+allocateReg (RealRegSingle r) f 
+	= f .&. complement (1 `shiftL` fromIntegral r)
+
+allocateReg _ _
+	= panic "RegAlloc.Linear.X86.FreeRegs.allocateReg: no reg"