X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=compiler%2FnativeGen%2FRegAllocColor.hs;h=51a0bffbc6c9f7efa4c6e8ff05497e202182bd17;hb=08652e67c4d5d9a40687f93c286021a867c1bca0;hp=35550dd095c11ab81addc2e53487644279a586b0;hpb=2381528a3b655af6becce8c8b130c63217992137;p=ghc-hetmet.git

diff --git a/compiler/nativeGen/RegAllocColor.hs b/compiler/nativeGen/RegAllocColor.hs
index 35550dd..51a0bff 100644
--- a/compiler/nativeGen/RegAllocColor.hs
+++ b/compiler/nativeGen/RegAllocColor.hs
@@ -1,10 +1,8 @@
+{-# OPTIONS -fno-warn-missing-signatures #-}
 -- | Graph coloring register allocator.
 --
--- TODO:
---	The function that choosing the potential spills could be a bit cleverer.
---	Colors in graphviz graphs could be nicer.
+-- TODO: The colors in graphviz graphs for x86_64 and ppc could be nicer.
 --
-{-# OPTIONS -fno-warn-missing-signatures #-}
 
 module RegAllocColor ( 
 	regAlloc,
@@ -17,6 +15,7 @@ import qualified GraphColor	as Color
 import RegLiveness
 import RegSpill
 import RegSpillClean
+import RegSpillCost
 import RegAllocStats
 -- import RegCoalesce
 import MachRegs
@@ -61,7 +60,7 @@ regAlloc dflags regsFree slotsFree code
 	return	( code_final
 		, reverse debug_codeGraphs )
 
-regAlloc_spin dflags (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs code
+regAlloc_spin dflags spinCount triv regsFree slotsFree debug_codeGraphs code
  = do
  	-- if any of these dump flags are turned on we want to hang on to
 	--	intermediate structures in the allocator - otherwise tell the
@@ -80,21 +79,8 @@ regAlloc_spin dflags (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs
 						$ uniqSetToList $ unionManyUniqSets $ eltsUFM regsFree)
 		$$ text "slotsFree   = " <> ppr (sizeUniqSet slotsFree))
 
-
-	-- Brig's algorithm does reckless coalescing for all but the first allocation stage
-	--	Doing this seems to reduce the number of reg-reg moves, but at the cost-
-	--	of creating more spills. Probably better just to stick with conservative 
-	--	coalescing in Color.colorGraph for now.
-	--
-	{- code_coalesced1	<- if (spinCount > 0) 
-				then regCoalesce code
-				else return code -}
-
-	let code_coalesced1	= code
-
-
  	-- build a conflict graph from the code.
-	graph		<- {-# SCC "BuildGraph" #-} buildGraph code_coalesced1
+	graph		<- {-# SCC "BuildGraph" #-} buildGraph code
 
 	-- VERY IMPORTANT:
 	--	We really do want the graph to be fully evaluated _before_ we start coloring.
@@ -104,11 +90,13 @@ regAlloc_spin dflags (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs
 	seqGraph graph `seq` return ()
 
 
-	-- build a map of how many instructions each reg lives for.
-	--	this is lazy, it won't be computed unless we need to spill
+	-- build a map of the cost of spilling each instruction
+	--	this will only actually be computed if we have to spill something.
+	let spillCosts	= foldl' plusSpillCostInfo zeroSpillCostInfo
+			$ map slurpSpillCostInfo code
 
-	let fmLife	= {-# SCC "LifetimeCount" #-} plusUFMs_C (\(r1, l1) (_, l2) -> (r1, l1 + l2))
-			$ map lifetimeCount code_coalesced1
+	-- the function to choose regs to leave uncolored
+	let spill	= chooseSpill spillCosts
 
 	-- record startup state
 	let stat1	=
@@ -116,12 +104,8 @@ regAlloc_spin dflags (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs
 		 then	Just $ RegAllocStatsStart
 		 	{ raLiveCmm	= code
 			, raGraph	= graph
-			, raLifetimes	= fmLife }
+			, raSpillCosts	= spillCosts }
 		 else	Nothing
-
-
-	-- the function to choose regs to leave uncolored
-	let spill	= chooseSpill_maxLife fmLife
 	
 	-- try and color the graph 
 	let (graph_colored, rsSpill, rmCoalesce)
@@ -135,15 +119,23 @@ regAlloc_spin dflags (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs
 	let patchF reg	= case lookupUFM rmCoalesce reg of
 				Just reg'	-> patchF reg'
 				Nothing		-> reg
-	let code_coalesced2
-			= map (patchEraseLive patchF) code_coalesced1
+	let code_coalesced
+			= map (patchEraseLive patchF) code
 
 
 	-- see if we've found a coloring
 	if isEmptyUniqSet rsSpill
 	 then do
+		-- if -fasm-lint is turned on then validate the graph
+		let graph_colored_lint	=
+			if dopt Opt_DoAsmLinting dflags
+				then Color.validateGraph (text "")
+					True 	-- require all nodes to be colored
+					graph_colored
+				else graph_colored
+
 		-- patch the registers using the info in the graph
-	 	let code_patched	= map (patchRegsFromGraph graph_colored) code_coalesced2
+	 	let code_patched	= map (patchRegsFromGraph graph_colored_lint) code_coalesced
 
 		-- clean out unneeded SPILL/RELOADs
 		let code_spillclean	= map cleanSpills code_patched
@@ -158,12 +150,13 @@ regAlloc_spin dflags (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs
 		-- record what happened in this stage for debugging
 		let stat		=
 			RegAllocStatsColored
-			{ raGraph	= graph_colored
-			, raCoalesced	= rmCoalesce
-			, raPatched	= code_patched
-			, raSpillClean	= code_spillclean
-			, raFinal	= code_final
-			, raSRMs	= foldl' addSRM (0, 0, 0) $ map countSRMs code_spillclean }
+			{ raGraph		= graph
+			, raGraphColored	= graph_colored_lint
+			, raCoalesced		= rmCoalesce
+			, raPatched		= code_patched
+			, raSpillClean		= code_spillclean
+			, raFinal		= code_final
+			, raSRMs		= foldl' addSRM (0, 0, 0) $ map countSRMs code_spillclean }
 
 
 		let statList =
@@ -175,12 +168,21 @@ regAlloc_spin dflags (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs
 
 		return	( code_final
 			, statList
-			, graph_colored)
+			, graph_colored_lint)
 
+	 -- we couldn't find a coloring, time to spill something
 	 else do
+		-- if -fasm-lint is turned on then validate the graph
+		let graph_colored_lint	=
+			if dopt Opt_DoAsmLinting dflags
+				then Color.validateGraph (text "")
+					False 	-- don't require nodes to be colored
+					graph_colored
+				else graph_colored
+
 	 	-- spill the uncolored regs
 		(code_spilled, slotsFree', spillStats)
-			<- regSpill code_coalesced2 slotsFree rsSpill
+			<- regSpill code_coalesced slotsFree rsSpill
 
 		-- recalculate liveness
 		let code_nat	= map stripLive code_spilled
@@ -189,10 +191,10 @@ regAlloc_spin dflags (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs
 		-- record what happened in this stage for debugging
 		let stat	=
 			RegAllocStatsSpill
-			{ raGraph	= graph_colored
+			{ raGraph	= graph_colored_lint
 			, raCoalesced	= rmCoalesce
 			, raSpillStats	= spillStats
-			, raLifetimes	= fmLife
+			, raSpillCosts	= spillCosts
 			, raSpilled	= code_spilled }
 			    	
 		let statList =
@@ -207,46 +209,7 @@ regAlloc_spin dflags (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs
 			statList
 			code_relive
 
- 
------
--- Simple maxconflicts isn't always good, because we
---	can naievely end up spilling vregs that only live for one or two instrs.
---	
-{-
-chooseSpill_maxConflicts
-	:: Color.Graph Reg RegClass Reg
-	-> Reg
-	
-chooseSpill_maxConflicts graph
- = let	node	= maximumBy 
- 			(\n1 n2 -> compare 
- 				(sizeUniqSet $ Color.nodeConflicts n1) 
-				(sizeUniqSet $ Color.nodeConflicts n2))
- 		$ eltsUFM $ Color.graphMap graph
-		
-   in	Color.nodeId node
--} 
-   
------
-chooseSpill_maxLife
-	:: UniqFM (Reg, Int)
-	-> Color.Graph Reg RegClass Reg
-	-> Reg
 
-chooseSpill_maxLife life graph
- = let	node	= maximumBy (\n1 n2 -> compare (getLife n1) (getLife n2))
-		$ eltsUFM $ Color.graphMap graph
-
-	-- Orphan vregs die in the same instruction they are born in.
-	--	They will be in the graph, but not in the liveness map.
-	--	Their liveness is 0.
-	getLife n
-	 = case lookupUFM life (Color.nodeId n) of
-	 	Just (_, l)	-> l
-		Nothing		-> 0
-
-   in	Color.nodeId node
-   
 
 -- | Build a graph from the liveness and coalesce information in this code.
 
@@ -346,11 +309,6 @@ patchRegsFromGraph graph code
    in	patchEraseLive patchF code
    
 
-plusUFMs_C  :: (elt -> elt -> elt) -> [UniqFM elt] -> UniqFM elt
-plusUFMs_C f maps
-	= foldl' (plusUFM_C f) emptyUFM maps
-
-
 -----
 -- for when laziness just isn't what you wanted...
 --