X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=compiler%2FnativeGen%2FRegAllocColor.hs;h=a2b98f1f6a31e32bc71dfac6ed57013f81a930de;hb=873dc895ab9c059fa80c34d43e13228c5049ae9d;hp=5a3401f1fdeb8cea5f6d32134a007af9b9dc0c90;hpb=682d5e9674ec8cf94b3af815a752fa03c9a9d6fe;p=ghc-hetmet.git diff --git a/compiler/nativeGen/RegAllocColor.hs b/compiler/nativeGen/RegAllocColor.hs index 5a3401f..a2b98f1 100644 --- a/compiler/nativeGen/RegAllocColor.hs +++ b/compiler/nativeGen/RegAllocColor.hs @@ -1,17 +1,10 @@ -- | Graph coloring register allocator. -- -- TODO: --- Live range splitting: --- At the moment regs that are spilled are spilled for all time, even though --- we might be able to allocate them a hardreg in different parts of the code. --- --- As we're aggressively coalescing before register allocation proper we're not currently --- using the coalescence information present in the graph. --- -- The function that choosing the potential spills could be a bit cleverer. --- -- Colors in graphviz graphs could be nicer. -- +{-# OPTIONS -fno-warn-missing-signatures #-} module RegAllocColor ( regAlloc, @@ -27,7 +20,6 @@ import RegSpillClean import RegAllocStats import MachRegs import MachInstrs -import RegCoalesce import PprMach import UniqSupply @@ -35,6 +27,7 @@ import UniqSet import UniqFM import Bag import Outputable +import DynFlags import Data.List import Data.Maybe @@ -51,7 +44,7 @@ maxSpinCount = 10 -- | The top level of the graph coloring register allocator. -- regAlloc - :: Bool -- ^ whether to generate RegAllocStats, or not. + :: DynFlags -> UniqFM (UniqSet Reg) -- ^ the registers we can use for allocation -> UniqSet Int -- ^ the set of available spill slots. -> [LiveCmmTop] -- ^ code annotated with liveness information. @@ -59,16 +52,25 @@ regAlloc ( [NatCmmTop] -- ^ code with registers allocated. , [RegAllocStats] ) -- ^ stats for each stage of allocation -regAlloc dump regsFree slotsFree code +regAlloc dflags regsFree slotsFree code = do - (code_final, debug_codeGraphs, graph_final) - <- regAlloc_spin dump 0 trivColorable regsFree slotsFree [] code + (code_final, debug_codeGraphs, _) + <- regAlloc_spin dflags 0 trivColorable regsFree slotsFree [] code return ( code_final , reverse debug_codeGraphs ) -regAlloc_spin dump (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs code +regAlloc_spin dflags (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs code = do + -- if any of these dump flags are turned on we want to hang on to + -- intermediate structures in the allocator - otherwise tell the + -- allocator to ditch them early so we don't end up creating space leaks. + let dump = or + [ dopt Opt_D_dump_asm_regalloc_stages dflags + , dopt Opt_D_dump_asm_stats dflags + , dopt Opt_D_dump_asm_conflicts dflags ] + + -- check that we're not running off down the garden path. when (spinCount > maxSpinCount) $ pprPanic "regAlloc_spin: max build/spill cycle count exceeded." @@ -79,11 +81,20 @@ regAlloc_spin dump (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs c $$ text "slotsFree = " <> ppr (sizeUniqSet slotsFree)) -- build a conflict graph from the code. - graph <- buildGraph code + graph <- {-# SCC "BuildGraph" #-} buildGraph code + + -- VERY IMPORTANT: + -- We really do want the graph to be fully evaluated _before_ we start coloring. + -- If we don't do this now then when the call to Color.colorGraph forces bits of it, + -- the heap will be filled with half evaluated pieces of graph and zillions of apply thunks. + -- + seqGraph graph `seq` return () + -- build a map of how many instructions each reg lives for. -- this is lazy, it won't be computed unless we need to spill - let fmLife = plusUFMs_C (\(r1, l1) (r2, l2) -> (r1, l1 + l2)) + + let fmLife = {-# SCC "LifetimeCount" #-} plusUFMs_C (\(r1, l1) (_, l2) -> (r1, l1 + l2)) $ map lifetimeCount code -- record startup state @@ -100,22 +111,33 @@ regAlloc_spin dump (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs c let spill = chooseSpill_maxLife fmLife -- try and color the graph - let (graph_colored, rsSpill) - = Color.colorGraph regsFree triv spill graph + let (graph_colored, rsSpill, rmCoalesce) + = {-# SCC "ColorGraph" #-} + Color.colorGraph + (dopt Opt_RegsIterative dflags) + regsFree triv spill graph + + -- rewrite regs in the code that have been coalesced + let patchF reg = case lookupUFM rmCoalesce reg of + Just reg' -> patchF reg' + Nothing -> reg + let code_coalesced + = map (patchEraseLive patchF) code + -- see if we've found a coloring if isEmptyUniqSet rsSpill then do -- patch the registers using the info in the graph - let code_patched = map (patchRegsFromGraph graph_colored) code + let code_patched = map (patchRegsFromGraph graph_colored) code_coalesced -- clean out unneeded SPILL/RELOADs let code_spillclean = map cleanSpills code_patched -- strip off liveness information - let code_nat = map stripLive code_patched + let code_nat = map stripLive code_spillclean - -- rewrite SPILL/REALOAD pseudos into real instructions + -- rewrite SPILL/RELOAD pseudos into real instructions let spillNatTop = mapGenBlockTop spillNatBlock let code_final = map spillNatTop code_nat @@ -123,21 +145,29 @@ regAlloc_spin dump (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs c let stat = RegAllocStatsColored { raGraph = graph_colored + , raCoalesced = rmCoalesce , raPatched = code_patched , raSpillClean = code_spillclean - , raFinal = code_final } + , raFinal = code_final + , raSRMs = foldl' addSRM (0, 0, 0) $ map countSRMs code_spillclean } - return ( code_final - , if dump - then [stat] ++ maybeToList stat1 ++ debug_codeGraphs + + let statList = + if dump then [stat] ++ maybeToList stat1 ++ debug_codeGraphs else [] + + -- space leak avoidance + seqList statList `seq` return () + + return ( code_final + , statList , graph_colored) else do -- spill the uncolored regs (code_spilled, slotsFree', spillStats) - <- regSpill code slotsFree rsSpill - + <- regSpill code_coalesced slotsFree rsSpill + -- recalculate liveness let code_nat = map stripLive code_spilled code_relive <- mapM regLiveness code_nat @@ -146,15 +176,21 @@ regAlloc_spin dump (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs c let stat = RegAllocStatsSpill { raGraph = graph_colored + , raCoalesced = rmCoalesce , raSpillStats = spillStats , raLifetimes = fmLife , raSpilled = code_spilled } - -- try again - regAlloc_spin dump (spinCount + 1) triv regsFree slotsFree' - (if dump + let statList = + if dump then [stat] ++ maybeToList stat1 ++ debug_codeGraphs - else []) + else [] + + -- space leak avoidance + seqList statList `seq` return () + + regAlloc_spin dflags (spinCount + 1) triv regsFree slotsFree' + statList code_relive @@ -206,16 +242,22 @@ buildGraph buildGraph code = do - -- Add the reg-reg conflicts to the graph - let conflictSets = unionManyBags (map slurpConflicts code) - let graph_conflict = foldrBag graphAddConflictSet Color.initGraph conflictSets + -- Slurp out the conflicts and reg->reg moves from this code + let (conflictList, moveList) = + unzip $ map slurpConflicts code + + -- Slurp out the spill/reload coalesces + let moveList2 = map slurpReloadCoalesce code + -- Add the reg-reg conflicts to the graph + let conflictBag = unionManyBags conflictList + let graph_conflict = foldrBag graphAddConflictSet Color.initGraph conflictBag -- Add the coalescences edges to the graph. - let coalesce = unionManyBags (map slurpJoinMovs code) - let graph_coalesce = foldrBag graphAddCoalesce graph_conflict coalesce + let moveBag = unionBags (unionManyBags moveList2) (unionManyBags moveList) + let graph_coalesce = foldrBag graphAddCoalesce graph_conflict moveBag - return $ graph_coalesce + return $ Color.validateGraph (text "urk") graph_coalesce -- | Add some conflict edges to the graph. @@ -249,10 +291,10 @@ graphAddCoalesce -> Color.Graph Reg RegClass Reg graphAddCoalesce (r1, r2) graph - | RealReg regno <- r1 + | RealReg _ <- r1 = Color.addPreference (regWithClass r2) r1 graph - | RealReg regno <- r2 + | RealReg _ <- r2 = Color.addPreference (regWithClass r1) r2 graph | otherwise @@ -285,12 +327,70 @@ patchRegsFromGraph graph code = pprPanic "patchRegsFromGraph: register mapping failed." ( text "There is no node in the graph for register " <> ppr reg $$ ppr code - $$ Color.dotGraph (\x -> text "white") trivColorable graph) - + $$ Color.dotGraph (\_ -> text "white") trivColorable graph) + in patchEraseLive patchF code plusUFMs_C :: (elt -> elt -> elt) -> [UniqFM elt] -> UniqFM elt plusUFMs_C f maps - = foldl (plusUFM_C f) emptyUFM maps - + = foldl' (plusUFM_C f) emptyUFM maps + + +----- +-- for when laziness just isn't what you wanted... +-- +seqGraph :: Color.Graph Reg RegClass Reg -> () +seqGraph graph = seqNodes (eltsUFM (Color.graphMap graph)) + +seqNodes :: [Color.Node Reg RegClass Reg] -> () +seqNodes ns + = case ns of + [] -> () + (n : ns) -> seqNode n `seq` seqNodes ns + +seqNode :: Color.Node Reg RegClass Reg -> () +seqNode node + = seqReg (Color.nodeId node) + `seq` seqRegClass (Color.nodeClass node) + `seq` seqMaybeReg (Color.nodeColor node) + `seq` (seqRegList (uniqSetToList (Color.nodeConflicts node))) + `seq` (seqRegList (uniqSetToList (Color.nodeExclusions node))) + `seq` (seqRegList (Color.nodePreference node)) + `seq` (seqRegList (uniqSetToList (Color.nodeCoalesce node))) + +seqReg :: Reg -> () +seqReg reg + = case reg of + RealReg _ -> () + VirtualRegI _ -> () + VirtualRegHi _ -> () + VirtualRegF _ -> () + VirtualRegD _ -> () + +seqRegClass :: RegClass -> () +seqRegClass c + = case c of + RcInteger -> () + RcFloat -> () + RcDouble -> () + +seqMaybeReg :: Maybe Reg -> () +seqMaybeReg mr + = case mr of + Nothing -> () + Just r -> seqReg r + +seqRegList :: [Reg] -> () +seqRegList rs + = case rs of + [] -> () + (r : rs) -> seqReg r `seq` seqRegList rs + +seqList :: [a] -> () +seqList ls + = case ls of + [] -> () + (r : rs) -> r `seq` seqList rs + +