X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=compiler%2FnativeGen%2FRegAllocColor.hs;h=d5ec7af8ebd84d90e780fa46f84fd91e7d9ece94;hb=29d909009d47c52c5f02630658f7422c634230ab;hp=933c8ab5d59696fe8fa12e926c52b5db696d378d;hpb=f0d0e9d63ee27a12e80b6f069be5e9d4b55ca545;p=ghc-hetmet.git

diff --git a/compiler/nativeGen/RegAllocColor.hs b/compiler/nativeGen/RegAllocColor.hs
index 933c8ab..d5ec7af 100644
--- a/compiler/nativeGen/RegAllocColor.hs
+++ b/compiler/nativeGen/RegAllocColor.hs
@@ -23,6 +23,7 @@ where
 import qualified GraphColor	as Color
 import RegLiveness
 import RegSpill
+import RegSpillClean
 import RegAllocStats
 import MachRegs
 import MachInstrs
@@ -50,22 +51,23 @@ maxSpinCount	= 10
 -- | The top level of the graph coloring register allocator.
 --	
 regAlloc
-	:: UniqFM (UniqSet Reg)				-- ^ the registers we can use for allocation
-	-> UniqSet Int					-- ^ the set of available spill slots.
-	-> [LiveCmmTop]					-- ^ code annotated with liveness information.
+	:: Bool				-- ^ whether to generate RegAllocStats, or not.
+	-> UniqFM (UniqSet Reg)		-- ^ the registers we can use for allocation
+	-> UniqSet Int			-- ^ the set of available spill slots.
+	-> [LiveCmmTop]			-- ^ code annotated with liveness information.
 	-> UniqSM 
-		( [NatCmmTop]				-- ^ code with registers allocated.
-		, [RegAllocStats] )			-- ^ stats for each stage of allocation
+		( [NatCmmTop]		-- ^ code with registers allocated.
+		, [RegAllocStats] )	-- ^ stats for each stage of allocation
 		
-regAlloc regsFree slotsFree code
+regAlloc dump regsFree slotsFree code
  = do
  	(code_final, debug_codeGraphs, graph_final)
-		<- regAlloc_spin 0 trivColorable regsFree slotsFree [] code
+		<- regAlloc_spin dump 0 trivColorable regsFree slotsFree [] code
 	
 	return	( code_final
-		, debug_codeGraphs )
+		, reverse debug_codeGraphs )
 
-regAlloc_spin (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs code 
+regAlloc_spin dump (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs code
  = do
 	-- check that we're not running off down the garden path.
 	when (spinCount > maxSpinCount)
@@ -79,11 +81,21 @@ regAlloc_spin (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs code
  	-- build a conflict graph from the code.
 	graph		<- buildGraph code
 
-	-- build a map of how many instructions each reg lives for
-	--	this lazy, it won't be computed unless we need to spill
+	-- build a map of how many instructions each reg lives for.
+	--	this is lazy, it won't be computed unless we need to spill
 	let fmLife	= plusUFMs_C (\(r1, l1) (r2, l2) -> (r1, l1 + l2))
 			$ map lifetimeCount code
 
+	-- record startup state
+	let stat1	=
+		if spinCount == 0
+		 then	Just $ RegAllocStatsStart
+		 	{ raLiveCmm	= code
+			, raGraph	= graph
+			, raLifetimes	= fmLife }
+		 else	Nothing
+
+
 	-- the function to choose regs to leave uncolored
 	let spill	= chooseSpill_maxLife fmLife
 	
@@ -96,17 +108,30 @@ regAlloc_spin (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs code
 	 then do
 		-- patch the registers using the info in the graph
 	 	let code_patched	= map (patchRegsFromGraph graph_colored) code
+
+		-- clean out unneeded SPILL/RELOADs
+		let code_spillclean	= map cleanSpills code_patched
+
+		-- strip off liveness information
 		let code_nat		= map stripLive code_patched
+
+		-- rewrite SPILL/REALOAD pseudos into real instructions
+		let spillNatTop		= mapGenBlockTop spillNatBlock
+		let code_final		= map spillNatTop code_nat
 		
 		-- record what happened in this stage for debugging
 		let stat		=
 			RegAllocStatsColored
-			{ raLiveCmm	= code
-			, raGraph	= graph_colored
-			, raPatchedCmm	= code_patched }
-
-		return	( code_nat
-			, debug_codeGraphs ++ [stat]
+			{ raGraph	= graph_colored
+			, raPatched	= code_patched
+			, raSpillClean	= code_spillclean
+			, raFinal	= code_final
+			, raSRMs	= foldl addSRM (0, 0, 0) $ map countSRMs code_spillclean }
+
+		return	( code_final
+			, if dump
+				then [stat] ++ maybeToList stat1 ++ debug_codeGraphs
+				else []
 			, graph_colored)
 
 	 else do
@@ -121,13 +146,16 @@ regAlloc_spin (spinCount :: Int) triv regsFree slotsFree debug_codeGraphs code
 		-- record what happened in this stage for debugging
 		let stat	=
 			RegAllocStatsSpill
-			{ raLiveCmm	= code_spilled
-			, raGraph	= graph_colored
-			, raSpillStats	= spillStats }
+			{ raGraph	= graph_colored
+			, raSpillStats	= spillStats
+			, raLifetimes	= fmLife
+			, raSpilled	= code_spilled }
 			    	
 		-- try again
-		regAlloc_spin (spinCount + 1) triv regsFree slotsFree' 
-			(debug_codeGraphs ++ [stat])
+		regAlloc_spin dump (spinCount + 1) triv regsFree slotsFree'
+			(if dump
+				then [stat] ++ maybeToList stat1 ++ debug_codeGraphs
+				else [])
 			code_relive
 
  
@@ -192,7 +220,7 @@ buildGraph code
 
 
 -- | Add some conflict edges to the graph.
---	Conflicts between virtual and real regs are recorded as exlusions.
+--	Conflicts between virtual and real regs are recorded as exclusions.
 --
 graphAddConflictSet 
 	:: UniqSet Reg
@@ -213,7 +241,7 @@ graphAddConflictSet set graph
    in	graph2
 	
 
--- | Add some coalesences edges to the graph
+-- | Add some coalesence edges to the graph
 --	Coalesences between virtual and real regs are recorded as preferences.
 --
 graphAddCoalesce