X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=compiler%2FnativeGen%2FRegAllocInfo.hs;h=da876c38fab721c346ce7148a39208d2f38c5a9f;hb=08652e67c4d5d9a40687f93c286021a867c1bca0;hp=376ea489b5b2374b4504b56aa121aea61a009a2d;hpb=7fc749a43b4b6b85d234fa95d4928648259584f4;p=ghc-hetmet.git

diff --git a/compiler/nativeGen/RegAllocInfo.hs b/compiler/nativeGen/RegAllocInfo.hs
index 376ea48..da876c3 100644
--- a/compiler/nativeGen/RegAllocInfo.hs
+++ b/compiler/nativeGen/RegAllocInfo.hs
@@ -1,3 +1,10 @@
+{-# OPTIONS -w #-}
+-- The above warning supression flag is a temporary kludge.
+-- While working on this module you are encouraged to remove it and fix
+-- any warnings in the module. See
+--     http://hackage.haskell.org/trac/ghc/wiki/Commentary/CodingStyle#Warnings
+-- for details
+
 -----------------------------------------------------------------------------
 --
 -- Machine-specific parts of the register allocator
@@ -6,13 +13,6 @@
 --
 -----------------------------------------------------------------------------
 
-{-# OPTIONS -w #-}
--- The above warning supression flag is a temporary kludge.
--- While working on this module you are encouraged to remove it and fix
--- any warnings in the module. See
---     http://hackage.haskell.org/trac/ghc/wiki/Commentary/CodingStyle#Warnings
--- for details
-
 #include "nativeGen/NCG.h"
 
 module RegAllocInfo (
@@ -42,7 +42,7 @@ import MachInstrs
 import MachRegs
 import Outputable
 import Constants	( rESERVED_C_STACK_BYTES )
-import FastTypes
+import FastBool
 
 -- -----------------------------------------------------------------------------
 -- RegUsage type
@@ -215,9 +215,9 @@ regUsage instr = case instr of
     GABS   sz src dst	-> mkRU [src] [dst]
     GNEG   sz src dst	-> mkRU [src] [dst]
     GSQRT  sz src dst	-> mkRU [src] [dst]
-    GSIN   sz src dst	-> mkRU [src] [dst]
-    GCOS   sz src dst	-> mkRU [src] [dst]
-    GTAN   sz src dst	-> mkRU [src] [dst]
+    GSIN   sz _ _ src dst	-> mkRU [src] [dst]
+    GCOS   sz _ _ src dst	-> mkRU [src] [dst]
+    GTAN   sz _ _ src dst	-> mkRU [src] [dst]
 #endif
 
 #if x86_64_TARGET_ARCH
@@ -599,9 +599,9 @@ patchRegs instr env = case instr of
     GABS sz src dst	-> GABS sz (env src) (env dst)
     GNEG sz src dst	-> GNEG sz (env src) (env dst)
     GSQRT sz src dst	-> GSQRT sz (env src) (env dst)
-    GSIN sz src dst	-> GSIN sz (env src) (env dst)
-    GCOS sz src dst	-> GCOS sz (env src) (env dst)
-    GTAN sz src dst	-> GTAN sz (env src) (env dst)
+    GSIN sz l1 l2 src dst	-> GSIN sz l1 l2 (env src) (env dst)
+    GCOS sz l1 l2 src dst	-> GCOS sz l1 l2 (env src) (env dst)
+    GTAN sz l1 l2 src dst	-> GTAN sz l1 l2 (env src) (env dst)
 #endif
 
 #if x86_64_TARGET_ARCH
@@ -774,7 +774,7 @@ isRegRegMove (MOV _ (OpReg r1) (OpReg r2)) = Just (r1,r2)
 #elif powerpc_TARGET_ARCH
 isRegRegMove (MR dst src) = Just (src,dst)
 #else
-#warning ToDo: isRegRegMove
+#error ToDo: isRegRegMove
 #endif
 isRegRegMove _ = Nothing
 
@@ -814,7 +814,7 @@ mkSpillInstr reg delta slot
                                     RcInteger -> I32;
 				    RcFloat   -> F32;
                                     RcDouble  -> F64}}
-                        in ST sz reg (fpRel (- off_w))
+                        in ST sz reg (fpRel (negate off_w))
 #endif
 #ifdef powerpc_TARGET_ARCH
     let sz = case regClass reg of
@@ -877,6 +877,8 @@ mkRegRegMoveInstr src dst
 #endif
 #elif powerpc_TARGET_ARCH
     = MR dst src
+#else
+#error ToDo: mkRegRegMoveInstr
 #endif
 
 mkBranchInstr