X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=compiler%2FnativeGen%2FRegAllocLinear.hs;h=bc538a82fa3f3f45da623d9afa3b703f924fce22;hb=e6748917380ae7826114c0801f1a61a4c7861bbc;hp=4b023c5e767b0c47b8286795255739ad99b4c4b7;hpb=f1d525d1f140bb695cd3a746ba7dd16402868dde;p=ghc-hetmet.git

diff --git a/compiler/nativeGen/RegAllocLinear.hs b/compiler/nativeGen/RegAllocLinear.hs
index 4b023c5..bc538a8 100644
--- a/compiler/nativeGen/RegAllocLinear.hs
+++ b/compiler/nativeGen/RegAllocLinear.hs
@@ -101,6 +101,7 @@ import UniqFM
 import UniqSupply
 import Outputable
 import State
+import FastString
 
 import Data.Maybe
 import Data.List
@@ -574,7 +575,7 @@ saveClobberedTemps clobbered dying =  do
 	recordSpill (SpillClobber temp)
 
 	let new_assign	= addToUFM assig temp (InBoth reg slot)
-	clobber new_assign (spill : COMMENT FSLIT("spill clobber") : instrs) rest
+	clobber new_assign (spill : COMMENT (fsLit "spill clobber") : instrs) rest
 
 clobberRegs :: [RegNo] -> RegM ()
 clobberRegs [] = return () -- common case
@@ -691,7 +692,7 @@ allocateRegsAndSpill reading keep spills alloc (r:rs) = do
 
     	        (spill_insn, slot) <- spillR (RealReg my_reg) temp_to_push_out
 		let spill_store	 = (if reading then id else reverse)
-					[ COMMENT FSLIT("spill alloc") 
+					[ COMMENT (fsLit "spill alloc") 
 					, spill_insn ]
 
 		-- record that this temp was spilled
@@ -723,7 +724,7 @@ loadTemp True vreg (Just (InMem slot)) hreg spills
  = do
  	insn <- loadR (RealReg hreg) slot
 	recordSpill (SpillLoad $ getUnique vreg)
-	return	$  COMMENT FSLIT("spill load") : insn : spills
+	return	$  COMMENT (fsLit "spill load") : insn : spills
 
 loadTemp _ _ _ _ spills =
    return spills
@@ -908,7 +909,7 @@ handleComponent delta instr (CyclicSCC ((vreg, (InReg sreg),dsts):rest))
 	 = do
 		restoreToReg 	<- loadR (RealReg reg) slot
 		moveInstr	<- makeMove delta vreg r mem
-		return $ [COMMENT FSLIT("spill join move"), restoreToReg, moveInstr]
+		return $ [COMMENT (fsLit "spill join move"), restoreToReg, moveInstr]
 
 	getRestoreMoves [InReg reg] slot
 		= loadR (RealReg reg) slot >>= return . (:[])