X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=compiler%2FnativeGen%2FSPARC%2FInstr.hs;h=00b57f9b06617aa3cb61d8d5e31b7f20857fb063;hb=335b9f366ac440259318777c4c07e4fa42fbbec6;hp=b21f9476ac3c6554ad12f09f809f6cce982c9966;hpb=42222f95a101fb3647f8728302bbf1098b74e59e;p=ghc-hetmet.git

diff --git a/compiler/nativeGen/SPARC/Instr.hs b/compiler/nativeGen/SPARC/Instr.hs
index b21f947..00b57f9 100644
--- a/compiler/nativeGen/SPARC/Instr.hs
+++ b/compiler/nativeGen/SPARC/Instr.hs
@@ -29,7 +29,9 @@ import SPARC.Imm
 import SPARC.AddrMode
 import SPARC.Cond
 import SPARC.Regs
+import SPARC.RegPlate
 import SPARC.Base
+import TargetReg
 import Instruction
 import RegClass
 import Reg
@@ -39,8 +41,7 @@ import BlockId
 import Cmm
 import FastString
 import FastBool
-
-import GHC.Exts
+import Outputable
 
 
 -- | Register or immediate
@@ -52,11 +53,11 @@ data RI
 --  	- a literal zero
 --	- register %g0, which is always zero.
 --
-riZero :: RI -> Bool
-riZero (RIImm (ImmInt 0))	    = True
-riZero (RIImm (ImmInteger 0))	    = True
-riZero (RIReg (RealReg 0))          = True
-riZero _			    = False
+riZero :: RI -> Bool	
+riZero (RIImm (ImmInt 0))			= True
+riZero (RIImm (ImmInteger 0))			= True
+riZero (RIReg (RegReal (RealRegSingle 0)))	= True
+riZero _					= False
 
 
 -- | Calculate the effective address which would be used by the
@@ -126,6 +127,11 @@ data Instr
 	| ST		Size Reg AddrMode 		-- size, src, dst
 
 	-- Int Arithmetic.
+	--	x:   add/sub with carry bit. 
+	--		In SPARC V9 addx and friends were renamed addc. 
+	--
+	--	cc:  modify condition codes
+	-- 
 	| ADD		Bool Bool Reg RI Reg 		-- x?, cc?, src1, src2, dst
 	| SUB		Bool Bool Reg RI Reg 		-- x?, cc?, src1, src2, dst
 
@@ -265,11 +271,9 @@ sparc_regUsageOfInstr instr
 interesting :: Reg -> Bool
 interesting reg
  = case reg of
- 	VirtualRegI  _	-> True
-	VirtualRegHi _	-> True
-	VirtualRegF  _	-> True
-	VirtualRegD  _	-> True
-	RealReg i	-> isFastTrue (freeReg i)
+	RegVirtual _			-> True
+	RegReal (RealRegSingle r1)	-> isFastTrue (freeReg r1)
+	RegReal (RealRegPair r1 _)	-> isFastTrue (freeReg r1)
 
 
 
@@ -365,17 +369,18 @@ sparc_mkSpillInstr
 sparc_mkSpillInstr reg _ slot
  = let	off     = spillSlotToOffset slot
         off_w	= 1 + (off `div` 4)
-        sz 	= case regClass reg of
+        sz 	= case targetClassOfReg reg of
 			RcInteger -> II32
 			RcFloat   -> FF32
 			RcDouble  -> FF64
+			_         -> panic "sparc_mkSpillInstr"
 		
     in ST sz reg (fpRel (negate off_w))
 
 
 -- | Make a spill reload instruction.
 sparc_mkLoadInstr
-	:: Reg		-- ^ register to load
+	:: Reg		-- ^ register to load into
 	-> Int		-- ^ current stack delta
 	-> Int		-- ^ spill slot to use
 	-> Instr
@@ -383,10 +388,11 @@ sparc_mkLoadInstr
 sparc_mkLoadInstr reg _ slot
   = let off     = spillSlotToOffset slot
 	off_w	= 1 + (off `div` 4)
-        sz	= case regClass reg of
+        sz	= case targetClassOfReg reg of
 			RcInteger -> II32
 			RcFloat   -> FF32
 			RcDouble  -> FF64
+			_         -> panic "sparc_mkLoadInstr"
 
         in LD sz (fpRel (- off_w)) reg
 
@@ -427,10 +433,17 @@ sparc_mkRegRegMoveInstr
 	-> Instr
 
 sparc_mkRegRegMoveInstr src dst
- = case regClass src of
-	RcInteger -> ADD  False False src (RIReg g0) dst
-	RcDouble  -> FMOV FF64 src dst
-	RcFloat   -> FMOV FF32 src dst
+	| srcClass	<- targetClassOfReg src
+	, dstClass	<- targetClassOfReg dst
+	, srcClass == dstClass
+	= case srcClass of
+		RcInteger -> ADD  False False src (RIReg g0) dst
+		RcDouble  -> FMOV FF64 src dst
+		RcFloat   -> FMOV FF32 src dst
+                _         -> panic "sparc_mkRegRegMoveInstr"
+	
+	| otherwise
+	= panic "SPARC.Instr.mkRegRegMoveInstr: classes of src and dest not the same"
 
 
 -- | Check whether an instruction represents a reg-reg move.