X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=compiler%2FnativeGen%2FSPARC%2FInstr.hs;h=30067825fab78f4453dc6fc346372b16c5717e36;hb=0bff9925654d75ef0fd8fb5d48b700337ebd8f47;hp=6c7af5b169d75f1a50d931fc3c653c29247f224b;hpb=547bf6827f1fc3f2fb31bc6323cc0d33b445f32a;p=ghc-hetmet.git

diff --git a/compiler/nativeGen/SPARC/Instr.hs b/compiler/nativeGen/SPARC/Instr.hs
index 6c7af5b..3006782 100644
--- a/compiler/nativeGen/SPARC/Instr.hs
+++ b/compiler/nativeGen/SPARC/Instr.hs
@@ -16,6 +16,8 @@ module SPARC.Instr (
 	fpRelEA,
 	moveSp,
 	
+	isUnconditionalJump,
+	
 	Instr(..),
 	maxSpillSlots
 )
@@ -69,6 +71,17 @@ moveSp :: Int -> Instr
 moveSp n
    = ADD False False sp (RIImm (ImmInt (n * wordLength))) sp
 
+-- | An instruction that will cause the one after it never to be exectuted
+isUnconditionalJump :: Instr -> Bool
+isUnconditionalJump ii
+ = case ii of
+ 	CALL{}		-> True
+	JMP{}		-> True
+	JMP_TBL{}	-> True
+	BI ALWAYS _ _	-> True
+	BF ALWAYS _ _ 	-> True
+	_		-> False
+
 
 -- | instance for sparc instruction set
 instance Instruction Instr where
@@ -113,6 +126,11 @@ data Instr
 	| ST		Size Reg AddrMode 		-- size, src, dst
 
 	-- Int Arithmetic.
+	--	x:   add/sub with carry bit. 
+	--		In SPARC V9 addx and friends were renamed addc. 
+	--
+	--	cc:  modify condition codes
+	-- 
 	| ADD		Bool Bool Reg RI Reg 		-- x?, cc?, src1, src2, dst
 	| SUB		Bool Bool Reg RI Reg 		-- x?, cc?, src1, src2, dst