X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=doc%2Fatmel.txt;h=58ca1a375f903e597a74ef06f052d0926530ed57;hb=5aeb7bdf450ed5f7848218e1e33494ce4edd7858;hp=175fe1bb497bf9182a1f6c76abf1cb7d1aa80626;hpb=bd58f393d7c3a4c82141138315feb0f5179ee0ab;p=slipway.git

diff --git a/doc/atmel.txt b/doc/atmel.txt
index 175fe1b..58ca1a3 100644
--- a/doc/atmel.txt
+++ b/doc/atmel.txt
@@ -31,7 +31,11 @@ Corrections
   This will assist in merging changes made in disjoint derivitaves.
 
     2005.08.12  [gosset]  Initial revision
-
+    2006.03.12  [megacz]  Swapped {L1,L0}->W, FB->{L0,L1}, {H0->L0,H1->L1}
+    2006.03.13  [megacz]  Fixed lowest bit of z=00000000; it should be "1"
+    2006.03.13  [megacz]  Corrected meaning of z-octet bits 2-4 in IOBs
+    2006.03.13  [megacz]  Added constant zeroes in IOB section
+    2006.04.15  [megacz]  un-swapped FB->{L0,L1}
 
 Background
 
@@ -105,23 +109,23 @@ Cartesian Resources
   +----+--------+--------+--------+--------+--------+--------+--------+--------+
   |Z3:0|                           D  octet                                    |
   +----+--------+--------+--------+--------+--------+--------+--------+--------+
-  |0000| V4->L4 | H4->L4 | FB->L2 | FB->L3 | FB->L1 | FB->L0 | FB->L4 |   0    |
+  |0000| V4->L4 | H4->L4 | FB->L2 | FB->L3 | FB->L1 | FB->L0 | FB->L4 |   1    |
   +----+--------+--------+--------+--------+--------+--------+--------+--------+
   |0001| ZM->R  | YL->R  | WZ->WM | FB->WM | ZM->C  | ZM->FB |  C->XO |  C->YO |
   +----+--------+--------+--------+--------+--------+--------+--------+--------+
   |0010| L4->Z  | L4->Y  | L3->Z  | L2->Z  | L1->Z  | L0->Z  | V4->OE | H4->OE |
   +----+--------+--------+--------+--------+--------+--------+--------+--------+
-  |0011| L2->W  | L3->W  | L4->W  | L4->X  | L1->W  | L0->W  |H2a<>V2a|H3b<>V3b|
+  |0011| L2->W  | L3->W  | L4->W  | L4->X  | L0->W  | L1->W  |H2a<>V2a|H3b<>V3b|
   +----+--------+--------+--------+--------+--------+--------+--------+--------+
-  |0100|  N->Y  |  S->Y  |  W->Y  |  E->Y  | L3->Y  | L2->Y  | L1->Y  | L0->Y  |
+  |0100|  N->Y  |  S->Y  |  W->Y  |  E->Y  | L0->Y  | L1->Y  | L2->Y  | L3->Y  |
   +----+--------+--------+--------+--------+--------+--------+--------+--------+
-  |0101| SW->X  | NE->X  | SE->X  | NW->X  | L3->X  | L2->X  | L1->X  | L0->X  |
+  |0101| SW->X  | NE->X  | SE->X  | NW->X  | L0->X  | L1->X  | L2->X  | L3->X  |
   +----+--------+--------+--------+--------+--------+--------+--------+--------+
   |0110|                  X-LUT truth table, inverted                          |
   +----+--------+--------+--------+--------+--------+--------+--------+--------+
   |0111|                  Y-LUT truth table, inverted                          |
   +----+--------+--------+--------+--------+--------+--------+--------+--------+
-  |1000| V3->L3 | H3->L3 | H2->L2 | V2->L2 | V1->L1 | H1->L1 | V0->L0 | H0->L0 |
+  |1000| V3->L3 | H3->L3 | H2->L2 | V2->L2 | V1->L1 | H0->L0 | V0->L0 | H1->L1 |
   +----+--------+--------+--------+--------+--------+--------+--------+--------+
   |1001|H1a<>V1a|H0a<>V0a|H0b<>V0b|H4a<>V4a|H4b<>V4b|H1b<>V1b|H3a<>V3a|H2b<>V2b|
   +----+--------+--------+--------+--------+--------+--------+--------+--------+
@@ -233,8 +237,10 @@ Block Memories
 I/O Blocks
 
   The Z octet for I/O resources always its most significant three bits
-  set to 011.  The next two bits are either 01 for a primary IOB or 10
-  for a secondary.
+  set to 011.  The next bit is 1 for North/South IO Blocks and 0 for
+  East/West IO Blocks.  The next bit is always 0, and the bit
+  following that is set to 0 for primary (orthogonally connected)
+  IOBs, 1 for secondary (diagonally connected) IOBs.
 
       S  = Sector wires of this cell
       S+ = Sector wires of next cell
@@ -252,15 +258,15 @@ I/O Blocks
   +--------+--------+--------+------+-------+-------+--------+--------+--------+
   |Z octet |                         D  octet                                  |
   +--------+--------+--------+------+-------+-------+--------+--------+--------+
-  |011__000| Schmit |      Slew     |~G2->CR|       |       Pull      |        |
+  |011_0_00| Schmit |      Slew     |~G2->CR|   0   |       Pull      |    0   |
   +--------+--------+--------+------+-------+-------+--------+--------+--------+
-  |011__001|REG->OUT|        |  OE  |              Output Mux                  |
+  |011_0_01|REG->OUT|    0   |  OE  |              Output Mux                  |
   +--------+--------+--------+------+-------+-------+--------+--------+--------+
   |011_0010|      Added Delay (primary)     |PRI->S-| PRI->G+| PRI->G | PRI->S |
   +--------+--------+--------+------+-------+-------+--------+--------+--------+
-  |011_1010|      Added Delay (secondary)   |SND->S | SND->S+|PRI->REG|SND->REG|
+  |011_0110|      Added Delay (secondary)   |SND->S | SND->S+|PRI->REG|SND->REG|
   +--------+--------+--------+------+-------+-------+--------+--------+--------+
-  |011__011|  OEM   | USEOEM |                   OEM                           |
+  |011_0_11|  OEM   | USEOEM |                   OEM                           |
   +--------+--------+--------+------+-------+-------+--------+--------+--------+