X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=ghc%2Fcompiler%2FnativeGen%2FAsmRegAlloc.lhs;h=90b379a8b88877b6f3e1bc0f5d64d3acebee5a2e;hb=553e90d9a32ee1b1809430f260c401cc4169c6c7;hp=d9e6cf21b5ece80c871147721c90bdd8552e0c78;hpb=6a3f5f6beed9cec42c4b3a1b7cabc1809c838562;p=ghc-hetmet.git

diff --git a/ghc/compiler/nativeGen/AsmRegAlloc.lhs b/ghc/compiler/nativeGen/AsmRegAlloc.lhs
index d9e6cf2..90b379a 100644
--- a/ghc/compiler/nativeGen/AsmRegAlloc.lhs
+++ b/ghc/compiler/nativeGen/AsmRegAlloc.lhs
@@ -14,13 +14,12 @@ import PprMach		( pprInstr )	-- Just for debugging
 import MachRegs
 import RegAllocInfo
 
-import FiniteMap	( FiniteMap, emptyFM, addListToFM, delListFromFM, 
-			  lookupFM, keysFM, eltsFM, mapFM, addToFM_C, addToFM,
-			  listToFM, fmToList, lookupWithDefaultFM )
-import Unique		( mkBuiltinUnique )
-import OrdList		( unitOL, appOL, fromOL, concatOL )
+import FiniteMap	( FiniteMap, emptyFM, 
+			  lookupFM, eltsFM, addToFM_C, addToFM,
+			  listToFM, fmToList )
+import OrdList		( fromOL )
 import Outputable
-import Unique		( Unique, Uniquable(..), mkPseudoUnique3 )
+import Unique		( mkPseudoUnique3 )
 import CLabel		( CLabel, pprCLabel )
 import FastTypes
 
@@ -72,7 +71,7 @@ runRegAllocate regs find_reserve_regs instrs
               $$
               (text "code = ")
               $$
-              (vcat (map pprInstr flatInstrs))
+              (vcat (map (docToSDoc.pprInstr) flatInstrs))
             )
     tryGeneral (resv:resvs)
        = case generalAlloc resv of
@@ -272,7 +271,7 @@ spill slot numbers for the uniques.
 insertSpillCode :: [Instr] -> [Instr]
 insertSpillCode insns
    = let uniques_in_insns
-            = map getUnique 
+            = map getVRegUnique 
                   (regSetToList 
                      (foldl unionRegSets emptyRegSet 
                             (map vregs_in_insn insns)))
@@ -280,7 +279,7 @@ insertSpillCode insns
             = case regUsage i of
                  RU rds wrs -> filterRegSet isVirtualReg 
                                              (rds `unionRegSets` wrs)
-         vreg_to_slot_map :: FiniteMap Unique Int
+         vreg_to_slot_map :: FiniteMap VRegUnique Int
          vreg_to_slot_map
             = listToFM (zip uniques_in_insns [0..])
 
@@ -298,7 +297,7 @@ insertSpillCode insns
 -- to the stack pointer, as opposed to the frame pointer.  The other is a 
 -- counter, used to manufacture new temporary register names.
 
-patchInstr :: FiniteMap Unique Int -> (Int,Int) -> Instr -> ((Int,Int), [Instr])
+patchInstr :: FiniteMap VRegUnique Int -> (Int,Int) -> Instr -> ((Int,Int), [Instr])
 patchInstr vreg_to_slot_map (delta,ctr) instr
 
  | null memSrcs && null memDsts 
@@ -331,13 +330,15 @@ patchInstr vreg_to_slot_map (delta,ctr) instr
            | isVirtualReg vreg
            = case [vi | (vreg', vi) <- vreg_env, vreg' == vreg] of
                 [i] -> case regClass vreg of
-                          RcInteger -> VirtualRegI (mkPseudoUnique3 i)
-                          RcFloat   -> VirtualRegF (mkPseudoUnique3 i)
-                          RcDouble  -> VirtualRegD (mkPseudoUnique3 i)
+                          RcInteger -> VirtualRegI (pseudoVReg i)
+                          RcFloat   -> VirtualRegF (pseudoVReg i)
+                          RcDouble  -> VirtualRegD (pseudoVReg i)
                 _   -> pprPanic "patchInstr: unmapped VReg" (ppr vreg)
            | otherwise
            = vreg
 
+        pseudoVReg i = VRegUniqueLo (mkPseudoUnique3 i)
+
 	memSrcs   = filter isVirtualReg (regSetToList srcs)
 	memDsts   = filter isVirtualReg (regSetToList dsts)