X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=ghc%2Fcompiler%2FnativeGen%2FMachInstrs.hs;h=28e2578dc0de52a449d962214961d52bbb656c0d;hb=153b9cb9b11e05c4edb1b6bc0a7b972660e41f70;hp=b0b68e4df5119a48c97fedd8344f2aa2e50e5d8c;hpb=423d477bfecd490de1449c59325c8776f91d7aac;p=ghc-hetmet.git

diff --git a/ghc/compiler/nativeGen/MachInstrs.hs b/ghc/compiler/nativeGen/MachInstrs.hs
index b0b68e4..28e2578 100644
--- a/ghc/compiler/nativeGen/MachInstrs.hs
+++ b/ghc/compiler/nativeGen/MachInstrs.hs
@@ -35,7 +35,6 @@ module MachInstrs (
     ) where
 
 #include "HsVersions.h"
-#include "../includes/ghcconfig.h"
 
 import MachRegs
 import Cmm
@@ -465,6 +464,12 @@ bit or 64 bit precision.
 -- Other things.
 	| CLTD -- sign extend %eax into %edx:%eax
 
+	| FETCHGOT    Reg  -- pseudo-insn for position-independent code
+                           -- pretty-prints as
+                           --       call 1f
+                           -- 1:    popl %reg
+                           --       addl __GLOBAL_OFFSET_TABLE__+.-1b, %reg
+                    
 data Operand
   = OpReg  Reg	        -- register
   | OpImm  Imm	        -- immediate value
@@ -661,6 +666,10 @@ fPair other = pprPanic "fPair(sparc NCG)" (ppr other)
 	      | CRNOR   Int Int Int    -- condition register nor
 	      | MFCR    Reg            -- move from condition register
 	      
+	      | MFLR    Reg            -- move from link register
+	      | FETCHPC Reg            -- pseudo-instruction:
+	                               -- bcl to next insn, mflr reg
+	      
 condUnsigned GU = True
 condUnsigned LU = True
 condUnsigned GEU = True