X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=ghc%2Fcompiler%2FnativeGen%2FMachMisc.lhs;h=0d39e9cd21df77b2febb80b45a8b7a877c26ba28;hb=1f3a9da2d3b6dcaf0634b3d4f5dbe54f069eebb8;hp=58ce3b4c85beb3c596f45dbb43f68616c7890234;hpb=dcef38bab91d45b56f7cf3ceeec96303d93728bb;p=ghc-hetmet.git diff --git a/ghc/compiler/nativeGen/MachMisc.lhs b/ghc/compiler/nativeGen/MachMisc.lhs index 58ce3b4..0d39e9c 100644 --- a/ghc/compiler/nativeGen/MachMisc.lhs +++ b/ghc/compiler/nativeGen/MachMisc.lhs @@ -1,92 +1,72 @@ % -% (c) The AQUA Project, Glasgow University, 1993-1996 +% (c) The AQUA Project, Glasgow University, 1993-1998 % \section[MachMisc]{Description of various machine-specific things} \begin{code} -#include "HsVersions.h" #include "nativeGen/NCG.h" module MachMisc ( - fixedHdrSizeInWords, varHdrSizeInWords, - charLikeSize, intLikeSize, mutHS, dataHS, sizeOf, primRepToSize, eXTRA_STK_ARGS_HERE, volatileSaves, volatileRestores, - storageMgrInfo, smCAFlist, smOldLim, smOldMutables, - smStablePtrTable, - targetMaxDouble, targetMaxInt, targetMinDouble, targetMinInt, underscorePrefix, fmtAsmLbl, - cvtLitLit, exactLog2, Instr(..), IF_ARCH_i386(Operand(..) COMMA,) Cond(..), - Size(..) - + Size(..), + IF_ARCH_i386(i386_insert_ffrees COMMA,) + #if alpha_TARGET_ARCH , RI(..) #endif #if i386_TARGET_ARCH #endif #if sparc_TARGET_ARCH - , RI(..), riZero + RI(..), riZero, fpRelEA, moveSp, fPair #endif ) where -IMP_Ubiq(){-uitous-} -IMPORT_DELOOPER(AbsCLoop) ( fixedHdrSizeInWords, varHdrSizeInWords ) -- paranoia -IMPORT_DELOOPER(NcgLoop) ( underscorePrefix, fmtAsmLbl ) -- paranoia -IMPORT_1_3(Char(isDigit)) +#include "HsVersions.h" +-- #include "config.h" import AbsCSyn ( MagicId(..) ) import AbsCUtils ( magicIdPrimRep ) -import CLabel ( CLabel ) -import CmdLineOpts ( opt_SccProfilingOn ) +import CLabel ( CLabel, isAsmTemp ) import Literal ( mkMachInt, Literal(..) ) import MachRegs ( stgReg, callerSaves, RegLoc(..), - Imm(..), Reg(..) -#if __GLASGOW_HASKELL__ >= 202 - ) -import qualified MachRegs (Addr) -#define MachRegsAddr MachRegs.Addr -#else - , Addr(..) + Imm(..), Reg(..), + MachRegsAddr(..) +# if sparc_TARGET_ARCH + ,fp, sp +# endif ) -#define MachRegsAddr Addr -#endif - -import OrdList ( OrdList ) import PrimRep ( PrimRep(..) ) -import SMRep ( SMRep(..), SMSpecRepKind(..), SMUpdateKind(..) ) -import Stix ( StixTree(..), StixReg(..), sStLitLbl, - CodeSegment - ) -import Util ( panic ) +import SMRep ( SMRep(..) ) +import Stix ( StixTree(..), StixReg(..), CodeSegment ) +import Panic ( panic ) +import Char ( isDigit ) +import GlaExts ( word2Int#, int2Word#, shiftRL#, and#, (/=#) ) +import Outputable ( text, pprPanic, ppr ) +import IOExts ( trace ) \end{code} \begin{code} -underscorePrefix :: Bool -- leading underscore on labels? - -underscorePrefix - = IF_ARCH_alpha(False - ,{-else-} IF_ARCH_i386( - IF_OS_linuxaout(True - , IF_OS_freebsd(True - , IF_OS_cygwin32(True - , IF_OS_bsdi(True - , {-otherwise-} False))) - ) - ,{-else-}IF_ARCH_sparc( - IF_OS_sunos4(True, {-otherwise-} False) - ,))) +underscorePrefix :: Bool -- leading underscore on assembler labels? + +#ifdef LEADING_UNDERSCORE +underscorePrefix = True +#else +underscorePrefix = False +#endif --------------------------- fmtAsmLbl :: String -> String -- for formatting labels @@ -99,47 +79,8 @@ fmtAsmLbl s -} '$' : s ,{-otherwise-} - s + '.':'L':s ) - ---------------------------- -cvtLitLit :: String -> String - --- --- Rather than relying on guessing, use FILE_SIZE to compute the --- _iob offsets. --- -cvtLitLit "stdin" = IF_ARCH_alpha("_iob+0" {-probably OK...-} - ,IF_ARCH_i386("_IO_stdin_" - ,IF_ARCH_sparc("__iob+0x0"{-probably OK...-} - ,))) - -cvtLitLit "stdout" = IF_ARCH_alpha("_iob+"++show (``FILE_SIZE''::Int) - ,IF_ARCH_i386("_IO_stdout_" - ,IF_ARCH_sparc("__iob+"++show (``FILE_SIZE''::Int) - ,))) -cvtLitLit "stderr" = IF_ARCH_alpha("_iob+"++show (2*(``FILE_SIZE''::Int)) - ,IF_ARCH_i386("_IO_stderr_" - ,IF_ARCH_sparc("__iob+"++show (2*(``FILE_SIZE''::Int)) - ,))) -{- -cvtLitLit "stdout" = IF_ARCH_alpha("_iob+56"{-dodgy *at best*...-} - ,IF_ARCH_i386("_IO_stdout_" - ,IF_ARCH_sparc("__iob+0x10"{-dodgy *at best*...-} - ,))) -cvtLitLit "stderr" = IF_ARCH_alpha("_iob+112"{-dodgy *at best*...-} - ,IF_ARCH_i386("_IO_stderr_" - ,IF_ARCH_sparc("__iob+0x20"{-dodgy *at best*...-} - ,))) --} -cvtLitLit s - | isHex s = s - | otherwise = error ("Native code generator can't handle ``" ++ s ++ "''") - where - isHex ('0':'x':xs) = all isHexDigit xs - isHex _ = False - -- Now, where have I seen this before? - isHexDigit c = isDigit c || c >= 'A' && c <= 'F' || c >= 'a' && c <= 'f' \end{code} % ---------------------------------------------------------------- @@ -152,63 +93,6 @@ eXTRA_STK_ARGS_HERE = IF_ARCH_alpha(0, IF_ARCH_i386(23{-6x4bytes-}, IF_ARCH_sparc(23,???))) \end{code} -% ---------------------------------------------------------------- - -@fixedHdrSizeInWords@ and @varHdrSizeInWords@: these are not dependent -on target architecture. -\begin{code} -fixedHdrSizeInWords :: Int - -fixedHdrSizeInWords - = 1{-info ptr-} + profFHS + parFHS + tickyFHS - -- obviously, we aren't taking non-sequential too seriously yet - where - profFHS = if opt_SccProfilingOn then 1 else 0 - parFHS = {-if PAR or GRAN then 1 else-} 0 - tickyFHS = {-if ticky ... then 1 else-} 0 - -varHdrSizeInWords :: SMRep -> Int{-in words-} - -varHdrSizeInWords sm - = case sm of - StaticRep _ _ -> 0 - SpecialisedRep _ _ _ _ -> 0 - GenericRep _ _ _ -> 0 - BigTupleRep _ -> 1 - MuTupleRep _ -> 2 {- (1 + GC_MUT_RESERVED_WORDS) -} - DataRep _ -> 1 - DynamicRep -> 2 - BlackHoleRep -> 0 - PhantomRep -> panic "MachMisc.varHdrSizeInWords:phantom" -\end{code} - -% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -Static closure sizes: -\begin{code} -charLikeSize, intLikeSize :: Int - -charLikeSize = blahLikeSize CharLikeRep -intLikeSize = blahLikeSize IntLikeRep - -blahLikeSize blah - = fromInteger (sizeOf PtrRep) - * (fixedHdrSizeInWords + varHdrSizeInWords blahLikeRep + 1) - where - blahLikeRep = SpecialisedRep blah 0 1 SMNormalForm - --------- -mutHS, dataHS :: StixTree - -mutHS = blah_hs (MuTupleRep 0) -dataHS = blah_hs (DataRep 0) - -blah_hs blah - = StInt (toInteger words) - where - words = fixedHdrSizeInWords + varHdrSizeInWords blah -\end{code} - % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Size of a @PrimRep@, in bytes. @@ -235,8 +119,8 @@ constants. \begin{code} volatileSaves, volatileRestores :: [MagicId] -> [StixTree] -save_cands = [BaseReg,SpA,SuA,SpB,SuB,Hp,HpLim,RetReg] -restore_cands = save_cands ++ [StkStubReg,StdUpdRetVecReg] +save_cands = [BaseReg,Sp,Su,SpLim,Hp,HpLim] +restore_cands = save_cands volatileSaves vols = map save ((filter callerSaves) (save_cands ++ vols)) @@ -267,27 +151,12 @@ ToDo: Fix!(JSM) \begin{code} targetMinDouble = MachDouble (-1.7976931348623157e+308) targetMaxDouble = MachDouble (1.7976931348623157e+308) -targetMinInt = mkMachInt (-2147483647) +targetMinInt = mkMachInt (-2147483648) targetMaxInt = mkMachInt 2147483647 \end{code} % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -Storage manager nonsense. Note that the indices are dependent on -the definition of the smInfo structure in SMinterface.lh - -\begin{code} -storageMgrInfo, smCAFlist, smOldMutables, smOldLim :: StixTree - -storageMgrInfo = sStLitLbl SLIT("StorageMgrInfo") -smCAFlist = StInd PtrRep (StIndex PtrRep storageMgrInfo (StInt SM_CAFLIST)) -smOldMutables = StInd PtrRep (StIndex PtrRep storageMgrInfo (StInt SM_OLDMUTABLES)) -smOldLim = StInd PtrRep (StIndex PtrRep storageMgrInfo (StInt SM_OLDLIM)) -smStablePtrTable = StInd PtrRep (StIndex PtrRep storageMgrInfo (StInt SM_STABLEPOINTERTABLE)) -\end{code} - -% - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - This algorithm for determining the $\log_2$ of exact powers of 2 comes from GCC. It requires bit manipulation primitives, and we use GHC extensions. Tough. @@ -295,7 +164,6 @@ extensions. Tough. \begin{code} w2i x = word2Int# x i2w x = int2Word# x -i2w_s x = (x::Int#) exactLog2 :: Integer -> Maybe Integer exactLog2 x @@ -309,10 +177,10 @@ exactLog2 x Just (toInteger (I# (pow2 x#))) } where - shiftr x y = shiftRA# x y + shiftr x y = shiftRL# x y pow2 x# | x# ==# 1# = 0# - | otherwise = 1# +# pow2 (w2i (i2w x# `shiftr` i2w_s 1#)) + | otherwise = 1# +# pow2 (w2i (i2w x# `shiftr` 1#)) \end{code} % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -388,6 +256,7 @@ data Size | L | F -- IEEE single-precision floating pt | DF -- IEEE single-precision floating pt + | F80 -- Intel 80-bit internal FP format; only used for spilling #endif #if sparc_TARGET_ARCH = B -- byte (signed) @@ -407,7 +276,7 @@ primRepToSize CodePtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( primRepToSize DataPtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,))) primRepToSize RetRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,))) primRepToSize CostCentreRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,))) -primRepToSize CharRep = IF_ARCH_alpha( BU, IF_ARCH_i386( L, IF_ARCH_sparc( BU,))) +primRepToSize CharRep = IF_ARCH_alpha( BU, IF_ARCH_i386( B, IF_ARCH_sparc( BU,))) primRepToSize IntRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,))) primRepToSize WordRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,))) primRepToSize AddrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,))) @@ -415,8 +284,13 @@ primRepToSize FloatRep = IF_ARCH_alpha( TF, IF_ARCH_i386( F, IF_ARCH_sparc( primRepToSize DoubleRep = IF_ARCH_alpha( TF, IF_ARCH_i386( DF,IF_ARCH_sparc( DF,))) primRepToSize ArrayRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,))) primRepToSize ByteArrayRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,))) +primRepToSize WeakPtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,))) +primRepToSize ForeignObjRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,))) primRepToSize StablePtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,))) -primRepToSize ForeignObjRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,))) +primRepToSize ThreadIdRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,))) +-- SUP: Wrong!!! Only for testing the rest of the NCG +primRepToSize Word64Rep = trace "primRepToSize: Word64Rep not handled" B +primRepToSize Int64Rep = trace "primRepToSize: Int64Rep not handled" B \end{code} %************************************************************************ @@ -437,6 +311,8 @@ data Instr String -- the literal string | DATA Size [Imm] + | DELTA Int -- specify current stack offset for + -- benefit of subsequent passes \end{code} \begin{code} @@ -447,10 +323,10 @@ data Instr -- Loads and stores. | LD Size Reg MachRegsAddr -- size, dst, src - | LDA Reg MachRegsAddr -- dst, src - | LDAH Reg MachRegsAddr -- dst, src - | LDGP Reg MachRegsAddr -- dst, src - | LDI Size Reg Imm -- size, dst, src + | LDA Reg MachRegsAddr -- dst, src + | LDAH Reg MachRegsAddr -- dst, src + | LDGP Reg MachRegsAddr -- dst, src + | LDI Size Reg Imm -- size, dst, src | ST Size Reg MachRegsAddr -- size, src, dst -- Int Arithmetic. @@ -522,6 +398,44 @@ data RI #endif {- alpha_TARGET_ARCH -} \end{code} +Intel, in their infinite wisdom, selected a stack model for floating +point registers on x86. That might have made sense back in 1979 -- +nowadays we can see it for the nonsense it really is. A stack model +fits poorly with the existing nativeGen infrastructure, which assumes +flat integer and FP register sets. Prior to this commit, nativeGen +could not generate correct x86 FP code -- to do so would have meant +somehow working the register-stack paradigm into the register +allocator and spiller, which sounds very difficult. + +We have decided to cheat, and go for a simple fix which requires no +infrastructure modifications, at the expense of generating ropey but +correct FP code. All notions of the x86 FP stack and its insns have +been removed. Instead, we pretend (to the instruction selector and +register allocator) that x86 has six floating point registers, %fake0 +.. %fake5, which can be used in the usual flat manner. We further +claim that x86 has floating point instructions very similar to SPARC +and Alpha, that is, a simple 3-operand register-register arrangement. +Code generation and register allocation proceed on this basis. + +When we come to print out the final assembly, our convenient fiction +is converted to dismal reality. Each fake instruction is +independently converted to a series of real x86 instructions. +%fake0 .. %fake5 are mapped to %st(0) .. %st(5). To do reg-reg +arithmetic operations, the two operands are pushed onto the top of the +FP stack, the operation done, and the result copied back into the +relevant register. There are only six %fake registers because 2 are +needed for the translation, and x86 has 8 in total. + +The translation is inefficient but is simple and it works. A cleverer +translation would handle a sequence of insns, simulating the FP stack +contents, would not impose a fixed mapping from %fake to %st regs, and +hopefully could avoid most of the redundant reg-reg moves of the +current translation. + +We might as well make use of whatever unique FP facilities Intel have +chosen to bless us with (let's not be churlish, after all). +Hence GLDZ and GLD1. Bwahahahahahahaha! + \begin{code} #if i386_TARGET_ARCH @@ -530,8 +444,8 @@ data RI -- Moves. | MOV Size Operand Operand - | MOVZX Size Operand Operand -- size is the size of operand 2 - | MOVSX Size Operand Operand -- size is the size of operand 2 + | MOVZxL Size Operand Operand -- size is the size of operand 1 + | MOVSxL Size Operand Operand -- size is the size of operand 1 -- Load effective address (also a very useful three-operand add instruction :-) @@ -555,57 +469,51 @@ data RI | XOR Size Operand Operand | NOT Size Operand | NEGI Size Operand -- NEG instruction (name clash with Cond) - | SHL Size Operand Operand -- 1st operand must be an Imm - | SAR Size Operand Operand -- 1st operand must be an Imm - | SHR Size Operand Operand -- 1st operand must be an Imm + | SHL Size Imm Operand -- Only immediate shifts allowed + | SAR Size Imm Operand -- Only immediate shifts allowed + | SHR Size Imm Operand -- Only immediate shifts allowed + | BT Size Imm Operand | NOP --- Float Arithmetic. -- ToDo for 386 +-- Float Arithmetic. --- Note that we cheat by treating F{ABS,MOV,NEG} of doubles as single instructions --- right up until we spit them out. +-- Note that we cheat by treating G{ABS,MOV,NEG} of doubles +-- as single instructions right up until we spit them out. + + -- all the 3-operand fake fp insns are src1 src2 dst + -- and furthermore are constrained to be fp regs only. + -- IMPORTANT: keep is_G_insn up to date with any changes here + | GMOV Reg Reg -- src(fpreg), dst(fpreg) + | GLD Size MachRegsAddr Reg -- src, dst(fpreg) + | GST Size Reg MachRegsAddr -- src(fpreg), dst + + | GLDZ Reg -- dst(fpreg) + | GLD1 Reg -- dst(fpreg) + + | GFTOD Reg Reg -- src(fpreg), dst(fpreg) + | GFTOI Reg Reg -- src(fpreg), dst(intreg) - | SAHF -- stores ah into flags - | FABS - | FADD Size Operand -- src - | FADDP - | FIADD Size MachRegsAddr -- src - | FCHS - | FCOM Size Operand -- src - | FCOS - | FDIV Size Operand -- src - | FDIVP - | FIDIV Size MachRegsAddr -- src - | FDIVR Size Operand -- src - | FDIVRP - | FIDIVR Size MachRegsAddr -- src - | FICOM Size MachRegsAddr -- src - | FILD Size MachRegsAddr Reg -- src, dst - | FIST Size MachRegsAddr -- dst - | FLD Size Operand -- src - | FLD1 - | FLDZ - | FMUL Size Operand -- src - | FMULP - | FIMUL Size MachRegsAddr -- src - | FRNDINT - | FSIN - | FSQRT - | FST Size Operand -- dst - | FSTP Size Operand -- dst - | FSUB Size Operand -- src - | FSUBP - | FISUB Size MachRegsAddr -- src - | FSUBR Size Operand -- src - | FSUBRP - | FISUBR Size MachRegsAddr -- src - | FTST - | FCOMP Size Operand -- src - | FUCOMPP - | FXCH - | FNSTSW - | FNOP + | GDTOF Reg Reg -- src(fpreg), dst(fpreg) + | GDTOI Reg Reg -- src(fpreg), dst(intreg) + | GITOF Reg Reg -- src(intreg), dst(fpreg) + | GITOD Reg Reg -- src(intreg), dst(fpreg) + + | GADD Size Reg Reg Reg -- src1, src2, dst + | GDIV Size Reg Reg Reg -- src1, src2, dst + | GSUB Size Reg Reg Reg -- src1, src2, dst + | GMUL Size Reg Reg Reg -- src1, src2, dst + + | GCMP Size Reg Reg -- src1, src2 + + | GABS Size Reg Reg -- src, dst + | GNEG Size Reg Reg -- src, dst + | GSQRT Size Reg Reg -- src, dst + | GSIN Size Reg Reg -- src, dst + | GCOS Size Reg Reg -- src, dst + | GTAN Size Reg Reg -- src, dst + + | GFREE -- do ffree on all x86 regs; an ugly hack -- Comparison | TEST Size Operand Operand @@ -616,6 +524,8 @@ data RI | PUSH Size Operand | POP Size Operand + | PUSHA + | POPA -- Jumping around. @@ -632,6 +542,40 @@ data Operand | OpImm Imm -- immediate value | OpAddr MachRegsAddr -- memory reference + +i386_insert_ffrees :: [Instr] -> [Instr] +i386_insert_ffrees insns + | any is_G_instr insns + = concatMap ffree_before_nonlocal_transfers insns + | otherwise + = insns + +ffree_before_nonlocal_transfers insn + = case insn of + CALL _ -> [GFREE, insn] + JMP (OpImm (ImmCLbl clbl)) | isAsmTemp clbl -> [insn] + JMP _ -> [GFREE, insn] + other -> [insn] + + +-- if you ever add a new FP insn to the fake x86 FP insn set, +-- you must update this too +is_G_instr :: Instr -> Bool +is_G_instr instr + = case instr of + GMOV _ _ -> True; GLD _ _ _ -> True; GST _ _ _ -> True; + GLDZ _ -> True; GLD1 _ -> True; + GFTOD _ _ -> True; GFTOI _ _ -> True; + GDTOF _ _ -> True; GDTOI _ _ -> True; + GITOF _ _ -> True; GITOD _ _ -> True; + GADD _ _ _ _ -> True; GDIV _ _ _ _ -> True + GSUB _ _ _ _ -> True; GMUL _ _ _ _ -> True + GCMP _ _ _ -> True; GABS _ _ _ -> True + GNEG _ _ _ -> True; GSQRT _ _ _ -> True + GSIN _ _ _ -> True; GCOS _ _ _ -> True; GTAN _ _ _ -> True; + GFREE -> panic "is_G_instr: GFREE (!)" + other -> False + #endif {- i386_TARGET_ARCH -} \end{code} @@ -685,7 +629,7 @@ data Operand | BI Cond Bool Imm -- cond, annul?, target | BF Cond Bool Imm -- cond, annul?, target - | JMP MachRegsAddr -- target + | JMP MachRegsAddr -- target | CALL Imm Int Bool -- target, args, terminal data RI = RIReg Reg @@ -695,8 +639,24 @@ riZero :: RI -> Bool riZero (RIImm (ImmInt 0)) = True riZero (RIImm (ImmInteger 0)) = True -riZero (RIReg (FixedReg ILIT(0))) = True +riZero (RIReg (RealReg 0)) = True riZero _ = False +-- Calculate the effective address which would be used by the +-- corresponding fpRel sequence. fpRel is in MachRegs.lhs, +-- alas -- can't have fpRelEA here because of module dependencies. +fpRelEA :: Int -> Reg -> Instr +fpRelEA n dst + = ADD False False fp (RIImm (ImmInt (n * BYTES_PER_WORD))) dst + +-- Code to shift the stack pointer by n words. +moveSp :: Int -> Instr +moveSp n + = ADD False False sp (RIImm (ImmInt (n * BYTES_PER_WORD))) sp + +-- Produce the second-half-of-a-double register given the first half. +fPair :: Reg -> Reg +fPair (RealReg n) | n >= 32 && n `mod` 2 == 0 = RealReg (n+1) +fPair other = pprPanic "fPair(sparc NCG)" (ppr other) #endif {- sparc_TARGET_ARCH -} \end{code}