X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=ghc%2Fcompiler%2FnativeGen%2FMachMisc.lhs;h=1d3c3acb0578c2e3c088354f84b2574b8685724e;hb=21934a0a7bb582b57d737164699548eae0399fb7;hp=a51a6073b4b5306b26a6a49d62cd538d1b8acbba;hpb=4eb2a52eaa775b70bd471abdf2d2ce11960d848f;p=ghc-hetmet.git

diff --git a/ghc/compiler/nativeGen/MachMisc.lhs b/ghc/compiler/nativeGen/MachMisc.lhs
index a51a607..1d3c3ac 100644
--- a/ghc/compiler/nativeGen/MachMisc.lhs
+++ b/ghc/compiler/nativeGen/MachMisc.lhs
@@ -724,12 +724,12 @@ fPair other = pprPanic "fPair(sparc NCG)" (ppr other)
 
 -- Loads and stores.
 
-	      | LD	Size Reg MachRegsAddr -- size, dst, src
-	      | ST	Size Reg MachRegsAddr -- size, src, dst 
-	      | STU	Size Reg MachRegsAddr -- size, src, dst 
-	      | LIS	Reg Imm -- dst, src
-	      | LI	Reg Imm -- dst, src
-	      | MR	Reg Reg -- dst, src -- also for fmr
+	      | LD	Size Reg MachRegsAddr -- Load size, dst, src
+	      | ST	Size Reg MachRegsAddr -- Store size, src, dst 
+	      | STU	Size Reg MachRegsAddr -- Store with Update size, src, dst 
+	      | LIS	Reg Imm -- Load Immediate Shifted dst, src
+	      | LI	Reg Imm -- Load Immediate dst, src
+	      | MR	Reg Reg -- Move Register dst, src -- also for fmr
 	      
 	      | CMP     Size Reg RI --- size, src1, src2
 	      | CMPL    Size Reg RI --- size, src1, src2
@@ -749,21 +749,26 @@ fPair other = pprPanic "fPair(sparc NCG)" (ppr other)
 	      | AND	Reg Reg RI -- dst, src1, src2
 	      | OR	Reg Reg RI -- dst, src1, src2
 	      | XOR	Reg Reg RI -- dst, src1, src2
+	      | XORIS	Reg Reg Imm -- XOR Immediate Shifted dst, src1, src2
 	      
 	      | NEG	Reg Reg
 	      | NOT	Reg Reg
 	      
-	      | SLW	Reg Reg RI
-	      | SRW	Reg Reg RI
-	      | SRAW	Reg Reg RI
+	      | SLW	Reg Reg RI	-- shift left word
+	      | SRW	Reg Reg RI	-- shift right word
+	      | SRAW	Reg Reg RI	-- shift right arithmetic word
 	      
 	      | FADD	Size Reg Reg Reg
 	      | FSUB	Size Reg Reg Reg
 	      | FMUL	Size Reg Reg Reg
 	      | FDIV	Size Reg Reg Reg
+	      | FNEG	Reg Reg	 -- negate is the same for single and double prec.
 	      
 	      | FCMP	Reg Reg
 	      
+	      | FCTIWZ	Reg Reg		-- convert to integer word
+					-- (but destination is a FP register)
+	      
 data RI = RIReg Reg
 	| RIImm Imm