X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=ghc%2Fcompiler%2FnativeGen%2FMachMisc.lhs;h=a641a8a32791ddf497527a492b334df59aa4414e;hb=553e90d9a32ee1b1809430f260c401cc4169c6c7;hp=83c0332e9a399591b78a81950a43eaaf7f29d869;hpb=559f7d8d6ca8c0b5630e3eb0f0fe716480134b08;p=ghc-hetmet.git diff --git a/ghc/compiler/nativeGen/MachMisc.lhs b/ghc/compiler/nativeGen/MachMisc.lhs index 83c0332..a641a8a 100644 --- a/ghc/compiler/nativeGen/MachMisc.lhs +++ b/ghc/compiler/nativeGen/MachMisc.lhs @@ -33,6 +33,10 @@ module MachMisc ( #if sparc_TARGET_ARCH RI(..), riZero, fpRelEA, moveSp, fPair #endif +#if powerpc_TARGET_ARCH + , RI(..) + , condUnsigned, condToSigned +#endif ) where #include "HsVersions.h" @@ -53,13 +57,15 @@ import PrimRep ( PrimRep(..) ) import Stix ( StixStmt(..), StixExpr(..), StixReg(..), CodeSegment, DestInfo(..) ) import Panic ( panic ) -import GlaExts import Outputable ( pprPanic, ppr, showSDoc ) -import IOExts ( trace ) import Config ( cLeadingUnderscore ) import FastTypes +import FastString -import Maybe ( catMaybes ) +import GLAEXTS +import TRACE ( trace ) + +import Maybes ( mapCatMaybes ) \end{code} \begin{code} @@ -70,11 +76,11 @@ underscorePrefix = (cLeadingUnderscore == "YES") fmtAsmLbl :: String -> String -- for formatting labels fmtAsmLbl s - = IF_ARCH_alpha( {- The alpha assembler likes temporary labels to look like $L123 instead of L123. (Don't toss the L, because then Lf28 turns into $f28.) -} + = IF_ARCH_alpha( '$' : s ,{-otherwise-} '.':'L':s @@ -88,7 +94,8 @@ where do we start putting the rest of them? \begin{code} eXTRA_STK_ARGS_HERE :: Int eXTRA_STK_ARGS_HERE - = IF_ARCH_alpha(0, IF_ARCH_i386(23{-6x4bytes-}, IF_ARCH_sparc(23,???))) + = IF_ARCH_alpha(0, IF_ARCH_i386(23{-6x4bytes-}, IF_ARCH_sparc(23, + IF_ARCH_powerpc( IF_OS_darwin(24,8{-SVR4 ABI: Linux-}), ???)))) \end{code} % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -106,13 +113,15 @@ volatileSaves, volatileRestores :: [MagicId] -> [StixStmt] volatileSaves = volatileSavesOrRestores True volatileRestores = volatileSavesOrRestores False -save_cands = [BaseReg,Sp,Su,SpLim,Hp,HpLim] +save_cands = [BaseReg,Sp,SpLim,Hp,HpLim] restore_cands = save_cands volatileSavesOrRestores do_saves vols - = catMaybes (map mkCode vols) + = mapCatMaybes mkCode vols where mkCode mid + | case mid of { BaseReg -> True; _ -> False } + = panic "volatileSavesOrRestores:BaseReg" | not (callerSaves mid) = Nothing | otherwise -- must be callee-saves ... @@ -177,13 +186,7 @@ exactLog2 x } where pow2 x# | x# ==# 1# = 0# - | otherwise = 1# +# pow2 (w2i (i2w x# `shiftr` 1#)) - -#if __GLASGOW_HASKELL__ >= 503 - shiftr x y = uncheckedShiftRL# x y -#else - shiftr x y = shiftRL# x y -#endif + | otherwise = 1# +# pow2 (w2i (i2w x# `shiftRL#` 1#)) \end{code} % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -237,6 +240,19 @@ data Cond | VC | VS #endif +#if powerpc_TARGET_ARCH + = ALWAYS + | EQQ + | GE + | GEU + | GTT + | GU + | LE + | LEU + | LTT + | LU + | NE +#endif deriving Eq -- to make an assertion work \end{code} @@ -266,7 +282,7 @@ data Size | DF -- IEEE single-precision floating pt | F80 -- Intel 80-bit internal FP format; only used for spilling #endif -#if sparc_TARGET_ARCH +#if sparc_TARGET_ARCH || powerpc_TARGET_ARCH = B -- byte (signed) | Bu -- byte (unsigned) | H -- halfword (signed, 2 bytes) @@ -278,36 +294,28 @@ data Size primRepToSize :: PrimRep -> Size -primRepToSize PtrRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, ))) -primRepToSize CodePtrRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, ))) -primRepToSize DataPtrRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, ))) -primRepToSize RetRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, ))) -primRepToSize CostCentreRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, ))) -primRepToSize CharRep = IF_ARCH_alpha(L, IF_ARCH_i386(L, IF_ARCH_sparc(W, ))) +primRepToSize PtrRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, IF_ARCH_powerpc(W, )))) +primRepToSize CodePtrRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, IF_ARCH_powerpc(W, )))) +primRepToSize DataPtrRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, IF_ARCH_powerpc(W, )))) +primRepToSize RetRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, IF_ARCH_powerpc(W, )))) +primRepToSize CostCentreRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, IF_ARCH_powerpc(W, )))) +primRepToSize CharRep = IF_ARCH_alpha(L, IF_ARCH_i386(L, IF_ARCH_sparc(W, IF_ARCH_powerpc(W, )))) -primRepToSize Int8Rep = IF_ARCH_alpha(B, IF_ARCH_i386(B, IF_ARCH_sparc(B, ))) -primRepToSize Int16Rep = IF_ARCH_alpha(err,IF_ARCH_i386(W, IF_ARCH_sparc(H, ))) +primRepToSize Int8Rep = IF_ARCH_alpha(B, IF_ARCH_i386(B, IF_ARCH_sparc(B, IF_ARCH_powerpc(B, )))) +primRepToSize Int16Rep = IF_ARCH_alpha(err,IF_ARCH_i386(W, IF_ARCH_sparc(H, IF_ARCH_powerpc(H, )))) where err = primRepToSize_fail "Int16Rep" -primRepToSize Int32Rep = IF_ARCH_alpha(L, IF_ARCH_i386(L, IF_ARCH_sparc(W, ))) -primRepToSize Word8Rep = IF_ARCH_alpha(Bu, IF_ARCH_i386(Bu, IF_ARCH_sparc(Bu, ))) -primRepToSize Word16Rep = IF_ARCH_alpha(err,IF_ARCH_i386(Wu, IF_ARCH_sparc(Hu, ))) +primRepToSize Int32Rep = IF_ARCH_alpha(L, IF_ARCH_i386(L, IF_ARCH_sparc(W, IF_ARCH_powerpc(W, )))) +primRepToSize Word8Rep = IF_ARCH_alpha(Bu, IF_ARCH_i386(Bu, IF_ARCH_sparc(Bu, IF_ARCH_powerpc(Bu, )))) +primRepToSize Word16Rep = IF_ARCH_alpha(err,IF_ARCH_i386(Wu, IF_ARCH_sparc(Hu, IF_ARCH_powerpc(Hu, )))) where err = primRepToSize_fail "Word16Rep" -primRepToSize Word32Rep = IF_ARCH_alpha(L, IF_ARCH_i386(Lu, IF_ARCH_sparc(W, ))) - -primRepToSize IntRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, ))) -primRepToSize WordRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, ))) -primRepToSize AddrRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, ))) -primRepToSize FloatRep = IF_ARCH_alpha(TF, IF_ARCH_i386(F, IF_ARCH_sparc(F, ))) -primRepToSize DoubleRep = IF_ARCH_alpha(TF, IF_ARCH_i386(DF, IF_ARCH_sparc(DF, ))) -primRepToSize ArrayRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, ))) -primRepToSize ByteArrayRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, ))) -primRepToSize PrimPtrRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, ))) -primRepToSize WeakPtrRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, ))) -primRepToSize ForeignObjRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, ))) -primRepToSize BCORep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, ))) -primRepToSize StablePtrRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, ))) -primRepToSize StableNameRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, ))) -primRepToSize ThreadIdRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, ))) +primRepToSize Word32Rep = IF_ARCH_alpha(L, IF_ARCH_i386(Lu, IF_ARCH_sparc(W, IF_ARCH_powerpc(W, )))) + +primRepToSize IntRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, IF_ARCH_powerpc(W, )))) +primRepToSize WordRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, IF_ARCH_powerpc(W, )))) +primRepToSize AddrRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, IF_ARCH_powerpc(W, )))) +primRepToSize FloatRep = IF_ARCH_alpha(TF, IF_ARCH_i386(F, IF_ARCH_sparc(F, IF_ARCH_powerpc(F, )))) +primRepToSize DoubleRep = IF_ARCH_alpha(TF, IF_ARCH_i386(DF, IF_ARCH_sparc(DF, IF_ARCH_powerpc(DF, )))) +primRepToSize StablePtrRep = IF_ARCH_alpha(Q, IF_ARCH_i386(L, IF_ARCH_sparc(W, IF_ARCH_powerpc(W, )))) primRepToSize Word64Rep = primRepToSize_fail "Word64Rep" primRepToSize Int64Rep = primRepToSize_fail "Int64Rep" @@ -318,7 +326,6 @@ primRepToSize_fail str ++ "Workaround: use -fvia-C.\n\t" ++ "Perhaps you should report it as a GHC bug,\n\t" ++ "to glasgow-haskell-bugs@haskell.org.") - \end{code} %************************************************************************ @@ -332,7 +339,7 @@ mostly all of @Instr@ is machine-specific. \begin{code} data Instr - = COMMENT FAST_STRING -- comment pseudo-op + = COMMENT FastString -- comment pseudo-op | SEGMENT CodeSegment -- {data,text} segment pseudo-op | LABEL CLabel -- global label pseudo-op | ASCII Bool -- True <=> needs backslash conversion @@ -423,7 +430,7 @@ data RI = RIReg Reg | RIImm Imm -#endif {- alpha_TARGET_ARCH -} +#endif /* alpha_TARGET_ARCH */ \end{code} Intel, in their infinite wisdom, selected a stack model for floating @@ -576,7 +583,7 @@ but we don't care, since it doesn't get used much. We hope. | JMP DestInfo Operand -- possible dests, target | JXX Cond CLabel -- target - | CALL Imm + | CALL (Either Imm Reg) -- Other things. @@ -624,7 +631,7 @@ is_G_instr instr GFREE -> panic "is_G_instr: GFREE (!)" other -> False -#endif {- i386_TARGET_ARCH -} +#endif /* i386_TARGET_ARCH */ \end{code} \begin{code} @@ -681,7 +688,7 @@ is_G_instr instr | BF Cond Bool Imm -- cond, annul?, target | JMP DestInfo MachRegsAddr -- target - | CALL Imm Int Bool -- target, args, terminal + | CALL (Either Imm Reg) Int Bool -- target, args, terminal data RI = RIReg Reg | RIImm Imm @@ -709,5 +716,74 @@ moveSp n fPair :: Reg -> Reg fPair (RealReg n) | n >= 32 && n `mod` 2 == 0 = RealReg (n+1) fPair other = pprPanic "fPair(sparc NCG)" (ppr other) -#endif {- sparc_TARGET_ARCH -} +#endif /* sparc_TARGET_ARCH */ +\end{code} + +\begin{code} +#ifdef powerpc_TARGET_ARCH +-- data Instr continues... + +-- Loads and stores. + + | LD Size Reg MachRegsAddr -- Load size, dst, src + | ST Size Reg MachRegsAddr -- Store size, src, dst + | STU Size Reg MachRegsAddr -- Store with Update size, src, dst + | LIS Reg Imm -- Load Immediate Shifted dst, src + | LI Reg Imm -- Load Immediate dst, src + | MR Reg Reg -- Move Register dst, src -- also for fmr + + | CMP Size Reg RI --- size, src1, src2 + | CMPL Size Reg RI --- size, src1, src2 + + | BCC Cond CLabel + | MTCTR Reg + | BCTR DestInfo + | BL Imm [Reg] -- with list of argument regs + | BCTRL [Reg] + + | ADD Reg Reg RI -- dst, src1, src2 + | SUBF Reg Reg Reg -- dst, src1, src2 ; dst = src2 - src1 + | MULLW Reg Reg RI + | DIVW Reg Reg Reg + | DIVWU Reg Reg Reg + + | AND Reg Reg RI -- dst, src1, src2 + | OR Reg Reg RI -- dst, src1, src2 + | XOR Reg Reg RI -- dst, src1, src2 + | XORIS Reg Reg Imm -- XOR Immediate Shifted dst, src1, src2 + + | NEG Reg Reg + | NOT Reg Reg + + | SLW Reg Reg RI -- shift left word + | SRW Reg Reg RI -- shift right word + | SRAW Reg Reg RI -- shift right arithmetic word + + | FADD Size Reg Reg Reg + | FSUB Size Reg Reg Reg + | FMUL Size Reg Reg Reg + | FDIV Size Reg Reg Reg + | FNEG Reg Reg -- negate is the same for single and double prec. + + | FCMP Reg Reg + + | FCTIWZ Reg Reg -- convert to integer word + -- (but destination is a FP register) + +data RI = RIReg Reg + | RIImm Imm + +condUnsigned GU = True +condUnsigned LU = True +condUnsigned GEU = True +condUnsigned LEU = True +condUnsigned _ = False + +condToSigned GU = GTT +condToSigned LU = LTT +condToSigned GEU = GE +condToSigned LEU = LE +condToSigned x = x +#endif /* powerpc_TARGET_ARCH */ \end{code} +