X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=ghc%2Fcompiler%2FnativeGen%2FMachMisc.lhs;h=d72de134ed9d792d27f6eca67dd62404b04bfe60;hb=e2a7f07969b47fef0cdf284e1bf98a0ad7b01d76;hp=3c593e0567c51d6522c88fb668a2ef84ab1e61e5;hpb=55400852aca70c1c43d559f445e6a92b9eba097a;p=ghc-hetmet.git

diff --git a/ghc/compiler/nativeGen/MachMisc.lhs b/ghc/compiler/nativeGen/MachMisc.lhs
index 3c593e0..d72de13 100644
--- a/ghc/compiler/nativeGen/MachMisc.lhs
+++ b/ghc/compiler/nativeGen/MachMisc.lhs
@@ -475,49 +475,34 @@ data RI
 
 -- Float Arithmetic. -- ToDo for 386
 
--- Note that we cheat by treating F{ABS,MOV,NEG} of doubles as single instructions
+-- Note that we cheat by treating G{ABS,MOV,NEG} of doubles as single instructions
 -- right up until we spit them out.
 
-	      | SAHF	      -- stores ah into flags
-    	      | FABS
-	      | FADD	      Size Operand -- src
-	      | FADDP
-	      | FIADD	      Size MachRegsAddr -- src
-    	      | FCHS
-    	      | FCOM	      Size Operand -- src
-    	      | FCOS
-	      | FDIV	      Size Operand -- src
-	      | FDIVP
-	      | FIDIV	      Size MachRegsAddr -- src
-	      | FDIVR	      Size Operand -- src
-	      | FDIVRP
-	      | FIDIVR	      Size MachRegsAddr -- src
-    	      | FICOM	      Size MachRegsAddr -- src
-    	      | FILD	      Size MachRegsAddr Reg -- src, dst
-    	      | FIST	      Size MachRegsAddr -- dst
-    	      | FLD	      Size Operand -- src
-    	      | FLD1
-    	      | FLDZ
-    	      | FMUL	      Size Operand -- src
-    	      | FMULP
-    	      | FIMUL	      Size MachRegsAddr -- src
-    	      | FRNDINT
-    	      | FSIN
-    	      | FSQRT
-    	      | FST	      Size Operand -- dst
-    	      | FSTP	      Size Operand -- dst
-	      | FSUB	      Size Operand -- src
-	      | FSUBP
-	      | FISUB	      Size MachRegsAddr -- src
-	      | FSUBR	      Size Operand -- src
-	      | FSUBRP
-	      | FISUBR	      Size MachRegsAddr -- src
-	      | FTST
-    	      | FCOMP	      Size Operand -- src
-    	      | FUCOMPP
-	      | FXCH
-	      | FNSTSW
-	      | FNOP
+              -- all the 3-operand fake fp insns are src1 src2 dst
+              -- and furthermore are constrained to be fp regs only.
+    	      | GMOV	      Reg Reg -- src(fpreg), dst(fpreg)
+              | GLD           Size MachRegsAddr Reg -- src, dst(fpreg)
+              | GST           Size Reg MachRegsAddr -- src(fpreg), dst
+
+    	      | GFTOD	      Reg Reg -- src(fpreg), dst(fpreg)
+              | GFTOI         Reg Reg -- src(fpreg), dst(intreg)
+
+    	      | GDTOF	      Reg Reg -- src(fpreg), dst(fpreg)
+              | GDTOI         Reg Reg -- src(fpreg), dst(intreg)
+
+              | GITOF         Reg Reg -- src(intreg), dst(fpreg)
+              | GITOD         Reg Reg -- src(intreg), dst(fpreg)
+
+	      | GADD	      Size Reg Reg Reg -- src1, src2, dst
+	      | GDIV	      Size Reg Reg Reg -- src1, src2, dst
+	      | GSUB	      Size Reg Reg Reg -- src1, src2, dst
+	      | GMUL	      Size Reg Reg Reg -- src1, src2, dst
+
+    	      | GCMP	      Size Reg Reg -- src1, src2
+
+     	      | GABS	      Size Reg Reg -- src, dst
+    	      | GNEG	      Size Reg Reg -- src, dst
+    	      | GSQRT	      Size Reg Reg -- src, dst
 
 -- Comparison