X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=ghc%2Fcompiler%2FnativeGen%2FMachMisc.lhs;h=db78cb446e5e00f80ce07260af8e72fd78572431;hb=111cee3f1ad93816cb828e38b38521d85c3bcebb;hp=4ec74c378c83e2d007c601802d52e717112babe0;hpb=438596897ebbe25a07e1c82085cfbc5bdb00f09e;p=ghc-hetmet.git diff --git a/ghc/compiler/nativeGen/MachMisc.lhs b/ghc/compiler/nativeGen/MachMisc.lhs index 4ec74c3..db78cb4 100644 --- a/ghc/compiler/nativeGen/MachMisc.lhs +++ b/ghc/compiler/nativeGen/MachMisc.lhs @@ -18,30 +18,32 @@ module MachMisc ( underscorePrefix, fmtAsmLbl, - cvtLitLit, exactLog2, + stixFor_stdout, stixFor_stderr, stixFor_stdin, + Instr(..), IF_ARCH_i386(Operand(..) COMMA,) Cond(..), - Size(..) - + Size(..), + IF_ARCH_i386(i386_insert_ffrees COMMA,) + #if alpha_TARGET_ARCH , RI(..) #endif #if i386_TARGET_ARCH #endif #if sparc_TARGET_ARCH - , RI(..), riZero + RI(..), riZero #endif ) where #include "HsVersions.h" ---#include "config.h" +-- #include "config.h" import AbsCSyn ( MagicId(..) ) import AbsCUtils ( magicIdPrimRep ) -import CLabel ( CLabel ) -import Const ( mkMachInt, Literal(..) ) +import CLabel ( CLabel, isAsmTemp ) +import Literal ( mkMachInt, Literal(..) ) import MachRegs ( stgReg, callerSaves, RegLoc(..), Imm(..), Reg(..), MachRegsAddr(..) @@ -49,9 +51,10 @@ import MachRegs ( stgReg, callerSaves, RegLoc(..), import PrimRep ( PrimRep(..) ) import SMRep ( SMRep(..) ) import Stix ( StixTree(..), StixReg(..), CodeSegment ) -import Util ( panic ) +import Panic ( panic ) import Char ( isDigit ) import GlaExts ( word2Int#, int2Word#, shiftRL#, and#, (/=#) ) +import Outputable ( text ) \end{code} \begin{code} @@ -74,10 +77,34 @@ fmtAsmLbl s -} '$' : s ,{-otherwise-} - s + '.':'L':s ) --------------------------- +stixFor_stdout, stixFor_stderr, stixFor_stdin :: StixTree +#if i386_TARGET_ARCH +-- Linux glibc 2 / libc6 +stixFor_stdout = StInd PtrRep (StLitLbl (text "stdout")) +stixFor_stderr = StInd PtrRep (StLitLbl (text "stderr")) +stixFor_stdin = StInd PtrRep (StLitLbl (text "stdin")) +#endif + +#if alpha_TARGET_ARCH +stixFor_stdout = error "stixFor_stdout: not implemented for Alpha" +stixFor_stderr = error "stixFor_stderr: not implemented for Alpha" +stixFor_stdin = error "stixFor_stdin: not implemented for Alpha" +#endif + +#if sparc_TARGET_ARCH +stixFor_stdout = error "stixFor_stdout: not implemented for Sparc" +stixFor_stderr = error "stixFor_stderr: not implemented for Sparc" +stixFor_stdin = error "stixFor_stdin: not implemented for Sparc" +#endif + +#if 0 +Here's some old stuff from which it shouldn't be too hard to +implement the above for Alpha/Sparc. + cvtLitLit :: String -> String -- @@ -85,36 +112,20 @@ cvtLitLit :: String -> String -- _iob offsets. -- cvtLitLit "stdin" = IF_ARCH_alpha("_iob+0" {-probably OK...-} - ,IF_ARCH_i386("_IO_stdin_" + ,IF_ARCH_i386("stdin" ,IF_ARCH_sparc("__iob+0x0"{-probably OK...-} ,))) cvtLitLit "stdout" = IF_ARCH_alpha("_iob+"++show (``FILE_SIZE''::Int) - ,IF_ARCH_i386("_IO_stdout_" + ,IF_ARCH_i386("stdout" ,IF_ARCH_sparc("__iob+"++show (``FILE_SIZE''::Int) ,))) cvtLitLit "stderr" = IF_ARCH_alpha("_iob+"++show (2*(``FILE_SIZE''::Int)) - ,IF_ARCH_i386("_IO_stderr_" + ,IF_ARCH_i386("stderr" ,IF_ARCH_sparc("__iob+"++show (2*(``FILE_SIZE''::Int)) ,))) -{- -cvtLitLit "stdout" = IF_ARCH_alpha("_iob+56"{-dodgy *at best*...-} - ,IF_ARCH_i386("_IO_stdout_" - ,IF_ARCH_sparc("__iob+0x10"{-dodgy *at best*...-} - ,))) -cvtLitLit "stderr" = IF_ARCH_alpha("_iob+112"{-dodgy *at best*...-} - ,IF_ARCH_i386("_IO_stderr_" - ,IF_ARCH_sparc("__iob+0x20"{-dodgy *at best*...-} - ,))) --} -cvtLitLit s - | isHex s = s - | otherwise = error ("Native code generator can't handle ``" ++ s ++ "''") - where - isHex ('0':'x':xs) = all isHexDigit xs - isHex _ = False - -- Now, where have I seen this before? - isHexDigit c = isDigit c || c >= 'A' && c <= 'F' || c >= 'a' && c <= 'f' +#endif + \end{code} % ---------------------------------------------------------------- @@ -290,6 +301,7 @@ data Size | L | F -- IEEE single-precision floating pt | DF -- IEEE single-precision floating pt + | F80 -- Intel 80-bit internal FP format; only used for spilling #endif #if sparc_TARGET_ARCH = B -- byte (signed) @@ -309,7 +321,7 @@ primRepToSize CodePtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( primRepToSize DataPtrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,))) primRepToSize RetRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,))) primRepToSize CostCentreRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,))) -primRepToSize CharRep = IF_ARCH_alpha( BU, IF_ARCH_i386( L, IF_ARCH_sparc( BU,))) +primRepToSize CharRep = IF_ARCH_alpha( BU, IF_ARCH_i386( B, IF_ARCH_sparc( BU,))) primRepToSize IntRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,))) primRepToSize WordRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,))) primRepToSize AddrRep = IF_ARCH_alpha( Q, IF_ARCH_i386( L, IF_ARCH_sparc( W ,))) @@ -340,6 +352,8 @@ data Instr String -- the literal string | DATA Size [Imm] + | DELTA Int -- specify current stack offset for + -- benefit of subsequent passes \end{code} \begin{code} @@ -425,6 +439,44 @@ data RI #endif {- alpha_TARGET_ARCH -} \end{code} +Intel, in their infinite wisdom, selected a stack model for floating +point registers on x86. That might have made sense back in 1979 -- +nowadays we can see it for the nonsense it really is. A stack model +fits poorly with the existing nativeGen infrastructure, which assumes +flat integer and FP register sets. Prior to this commit, nativeGen +could not generate correct x86 FP code -- to do so would have meant +somehow working the register-stack paradigm into the register +allocator and spiller, which sounds very difficult. + +We have decided to cheat, and go for a simple fix which requires no +infrastructure modifications, at the expense of generating ropey but +correct FP code. All notions of the x86 FP stack and its insns have +been removed. Instead, we pretend (to the instruction selector and +register allocator) that x86 has six floating point registers, %fake0 +.. %fake5, which can be used in the usual flat manner. We further +claim that x86 has floating point instructions very similar to SPARC +and Alpha, that is, a simple 3-operand register-register arrangement. +Code generation and register allocation proceed on this basis. + +When we come to print out the final assembly, our convenient fiction +is converted to dismal reality. Each fake instruction is +independently converted to a series of real x86 instructions. +%fake0 .. %fake5 are mapped to %st(0) .. %st(5). To do reg-reg +arithmetic operations, the two operands are pushed onto the top of the +FP stack, the operation done, and the result copied back into the +relevant register. There are only six %fake registers because 2 are +needed for the translation, and x86 has 8 in total. + +The translation is inefficient but is simple and it works. A cleverer +translation would handle a sequence of insns, simulating the FP stack +contents, would not impose a fixed mapping from %fake to %st regs, and +hopefully could avoid most of the redundant reg-reg moves of the +current translation. + +We might as well make use of whatever unique FP facilities Intel have +chosen to bless us with (let's not be churlish, after all). +Hence GLDZ and GLD1. Bwahahahahahahaha! + \begin{code} #if i386_TARGET_ARCH @@ -433,8 +485,8 @@ data RI -- Moves. | MOV Size Operand Operand - | MOVZX Size Operand Operand -- size is the size of operand 2 - | MOVSX Size Operand Operand -- size is the size of operand 2 + | MOVZxL Size Operand Operand -- size is the size of operand 1 + | MOVSxL Size Operand Operand -- size is the size of operand 1 -- Load effective address (also a very useful three-operand add instruction :-) @@ -458,57 +510,51 @@ data RI | XOR Size Operand Operand | NOT Size Operand | NEGI Size Operand -- NEG instruction (name clash with Cond) - | SHL Size Operand Operand -- 1st operand must be an Imm or CL - | SAR Size Operand Operand -- 1st operand must be an Imm or CL - | SHR Size Operand Operand -- 1st operand must be an Imm or CL + | SHL Size Imm Operand -- Only immediate shifts allowed + | SAR Size Imm Operand -- Only immediate shifts allowed + | SHR Size Imm Operand -- Only immediate shifts allowed + | BT Size Imm Operand | NOP --- Float Arithmetic. -- ToDo for 386 +-- Float Arithmetic. + +-- Note that we cheat by treating G{ABS,MOV,NEG} of doubles +-- as single instructions right up until we spit them out. --- Note that we cheat by treating F{ABS,MOV,NEG} of doubles as single instructions --- right up until we spit them out. + -- all the 3-operand fake fp insns are src1 src2 dst + -- and furthermore are constrained to be fp regs only. + -- IMPORTANT: keep is_G_insn up to date with any changes here + | GMOV Reg Reg -- src(fpreg), dst(fpreg) + | GLD Size MachRegsAddr Reg -- src, dst(fpreg) + | GST Size Reg MachRegsAddr -- src(fpreg), dst + + | GLDZ Reg -- dst(fpreg) + | GLD1 Reg -- dst(fpreg) - | SAHF -- stores ah into flags - | FABS - | FADD Size Operand -- src - | FADDP - | FIADD Size MachRegsAddr -- src - | FCHS - | FCOM Size Operand -- src - | FCOS - | FDIV Size Operand -- src - | FDIVP - | FIDIV Size MachRegsAddr -- src - | FDIVR Size Operand -- src - | FDIVRP - | FIDIVR Size MachRegsAddr -- src - | FICOM Size MachRegsAddr -- src - | FILD Size MachRegsAddr Reg -- src, dst - | FIST Size MachRegsAddr -- dst - | FLD Size Operand -- src - | FLD1 - | FLDZ - | FMUL Size Operand -- src - | FMULP - | FIMUL Size MachRegsAddr -- src - | FRNDINT - | FSIN - | FSQRT - | FST Size Operand -- dst - | FSTP Size Operand -- dst - | FSUB Size Operand -- src - | FSUBP - | FISUB Size MachRegsAddr -- src - | FSUBR Size Operand -- src - | FSUBRP - | FISUBR Size MachRegsAddr -- src - | FTST - | FCOMP Size Operand -- src - | FUCOMPP - | FXCH - | FNSTSW - | FNOP + | GFTOD Reg Reg -- src(fpreg), dst(fpreg) + | GFTOI Reg Reg -- src(fpreg), dst(intreg) + | GDTOF Reg Reg -- src(fpreg), dst(fpreg) + | GDTOI Reg Reg -- src(fpreg), dst(intreg) + + | GITOF Reg Reg -- src(intreg), dst(fpreg) + | GITOD Reg Reg -- src(intreg), dst(fpreg) + + | GADD Size Reg Reg Reg -- src1, src2, dst + | GDIV Size Reg Reg Reg -- src1, src2, dst + | GSUB Size Reg Reg Reg -- src1, src2, dst + | GMUL Size Reg Reg Reg -- src1, src2, dst + + | GCMP Size Reg Reg -- src1, src2 + + | GABS Size Reg Reg -- src, dst + | GNEG Size Reg Reg -- src, dst + | GSQRT Size Reg Reg -- src, dst + | GSIN Size Reg Reg -- src, dst + | GCOS Size Reg Reg -- src, dst + | GTAN Size Reg Reg -- src, dst + + | GFREE -- do ffree on all x86 regs; an ugly hack -- Comparison | TEST Size Operand Operand @@ -519,6 +565,8 @@ data RI | PUSH Size Operand | POP Size Operand + | PUSHA + | POPA -- Jumping around. @@ -535,6 +583,40 @@ data Operand | OpImm Imm -- immediate value | OpAddr MachRegsAddr -- memory reference + +i386_insert_ffrees :: [Instr] -> [Instr] +i386_insert_ffrees insns + | any is_G_instr insns + = concatMap ffree_before_nonlocal_transfers insns + | otherwise + = insns + +ffree_before_nonlocal_transfers insn + = case insn of + CALL _ -> [GFREE, insn] + JMP (OpImm (ImmCLbl clbl)) | isAsmTemp clbl -> [insn] + JMP _ -> [GFREE, insn] + other -> [insn] + + +-- if you ever add a new FP insn to the fake x86 FP insn set, +-- you must update this too +is_G_instr :: Instr -> Bool +is_G_instr instr + = case instr of + GMOV _ _ -> True; GLD _ _ _ -> True; GST _ _ _ -> True; + GLDZ _ -> True; GLD1 _ -> True; + GFTOD _ _ -> True; GFTOI _ _ -> True; + GDTOF _ _ -> True; GDTOI _ _ -> True; + GITOF _ _ -> True; GITOD _ _ -> True; + GADD _ _ _ _ -> True; GDIV _ _ _ _ -> True + GSUB _ _ _ _ -> True; GMUL _ _ _ _ -> True + GCMP _ _ _ -> True; GABS _ _ _ -> True + GNEG _ _ _ -> True; GSQRT _ _ _ -> True + GSIN _ _ _ -> True; GCOS _ _ _ -> True; GTAN _ _ _ -> True; + GFREE -> panic "is_G_instr: GFREE (!)" + other -> False + #endif {- i386_TARGET_ARCH -} \end{code}