X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=ghc%2Fcompiler%2FnativeGen%2FMachMisc.lhs;h=e58821036a47b346d448f98487a0e8f0113a845d;hb=5ec161b9994b21d94a1d494ea6a7e5c360075cd0;hp=40f7872b94bc9f1543fa087a8cbc98bd95afeebe;hpb=97906cfcc30dd591e840921d336fdabeb1b8a315;p=ghc-hetmet.git

diff --git a/ghc/compiler/nativeGen/MachMisc.lhs b/ghc/compiler/nativeGen/MachMisc.lhs
index 40f7872..e588210 100644
--- a/ghc/compiler/nativeGen/MachMisc.lhs
+++ b/ghc/compiler/nativeGen/MachMisc.lhs
@@ -76,11 +76,11 @@ underscorePrefix = (cLeadingUnderscore == "YES")
 fmtAsmLbl :: String -> String  -- for formatting labels
 
 fmtAsmLbl s
-  =  IF_ARCH_alpha(
      {- The alpha assembler likes temporary labels to look like $L123
 	instead of L123.  (Don't toss the L, because then Lf28
 	turns into $f28.)
      -}
+  =  IF_ARCH_alpha(
      '$' : s
      ,{-otherwise-}
      '.':'L':s
@@ -112,7 +112,7 @@ volatileSaves, volatileRestores :: [MagicId] -> [StixStmt]
 volatileSaves    = volatileSavesOrRestores True
 volatileRestores = volatileSavesOrRestores False
 
-save_cands    = [BaseReg,Sp,Su,SpLim,Hp,HpLim]
+save_cands    = [BaseReg,Sp,SpLim,Hp,HpLim]
 restore_cands = save_cands
 
 volatileSavesOrRestores do_saves vols
@@ -429,7 +429,7 @@ data RI
   = RIReg Reg
   | RIImm Imm
 
-#endif {- alpha_TARGET_ARCH -}
+#endif /* alpha_TARGET_ARCH */
 \end{code}
 
 Intel, in their infinite wisdom, selected a stack model for floating
@@ -630,7 +630,7 @@ is_G_instr instr
         GFREE -> panic "is_G_instr: GFREE (!)"
         other -> False
 
-#endif {- i386_TARGET_ARCH -}
+#endif /* i386_TARGET_ARCH */
 \end{code}
 
 \begin{code}
@@ -715,7 +715,7 @@ moveSp n
 fPair :: Reg -> Reg
 fPair (RealReg n) | n >= 32 && n `mod` 2 == 0  = RealReg (n+1)
 fPair other = pprPanic "fPair(sparc NCG)" (ppr other)
-#endif {- sparc_TARGET_ARCH -}
+#endif /* sparc_TARGET_ARCH */
 \end{code}
 
 \begin{code}
@@ -724,24 +724,24 @@ fPair other = pprPanic "fPair(sparc NCG)" (ppr other)
 
 -- Loads and stores.
 
-	      | LD	Size Reg MachRegsAddr -- size, dst, src
-	      | ST	Size Reg MachRegsAddr -- size, src, dst 
-	      | STU	Size Reg MachRegsAddr -- size, src, dst 
-	      | LIS	Reg Imm -- dst, src
-	      | LI	Reg Imm -- dst, src
-	      | MR	Reg Reg -- dst, src -- also for fmr
+	      | LD	Size Reg MachRegsAddr -- Load size, dst, src
+	      | ST	Size Reg MachRegsAddr -- Store size, src, dst 
+	      | STU	Size Reg MachRegsAddr -- Store with Update size, src, dst 
+	      | LIS	Reg Imm -- Load Immediate Shifted dst, src
+	      | LI	Reg Imm -- Load Immediate dst, src
+	      | MR	Reg Reg -- Move Register dst, src -- also for fmr
 	      
 	      | CMP     Size Reg RI --- size, src1, src2
 	      | CMPL    Size Reg RI --- size, src1, src2
 	      
 	      | BCC     Cond CLabel
 	      | MTCTR	Reg
-	      | BCTR
+	      | BCTR    DestInfo
 	      | BL	Imm [Reg]	-- with list of argument regs
 	      | BCTRL	[Reg]
 	      
 	      | ADD     Reg Reg RI -- dst, src1, src2    
-	      | SUBF    Reg Reg RI -- dst, src1, src2    
+	      | SUBF    Reg Reg Reg -- dst, src1, src2 ; dst = src2 - src1  
 	      | MULLW	Reg Reg RI
 	      | DIVW	Reg Reg Reg
 	      | DIVWU	Reg Reg Reg
@@ -749,21 +749,26 @@ fPair other = pprPanic "fPair(sparc NCG)" (ppr other)
 	      | AND	Reg Reg RI -- dst, src1, src2
 	      | OR	Reg Reg RI -- dst, src1, src2
 	      | XOR	Reg Reg RI -- dst, src1, src2
+	      | XORIS	Reg Reg Imm -- XOR Immediate Shifted dst, src1, src2
 	      
 	      | NEG	Reg Reg
 	      | NOT	Reg Reg
 	      
-	      | SLW	Reg Reg RI
-	      | SRW	Reg Reg RI
-	      | SRAW	Reg Reg RI
+	      | SLW	Reg Reg RI	-- shift left word
+	      | SRW	Reg Reg RI	-- shift right word
+	      | SRAW	Reg Reg RI	-- shift right arithmetic word
 	      
 	      | FADD	Size Reg Reg Reg
 	      | FSUB	Size Reg Reg Reg
 	      | FMUL	Size Reg Reg Reg
 	      | FDIV	Size Reg Reg Reg
+	      | FNEG	Reg Reg	 -- negate is the same for single and double prec.
 	      
 	      | FCMP	Reg Reg
 	      
+	      | FCTIWZ	Reg Reg		-- convert to integer word
+					-- (but destination is a FP register)
+	      
 data RI = RIReg Reg
 	| RIImm Imm
 
@@ -778,6 +783,6 @@ condToSigned LU = LTT
 condToSigned GEU = GE
 condToSigned LEU = LE
 condToSigned x = x
-#endif {- powerpc_TARGET_ARCH -}
+#endif /* powerpc_TARGET_ARCH */
 \end{code}