X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=ghc%2Fcompiler%2FnativeGen%2FMachRegs.lhs;h=bd72d6b4484c22181505d03bb025472be9de56d2;hb=7d446f085a1e5ce22b3a54b718e79a3da1bd8091;hp=7493de4e9f8afb23c678d67159a26dd17a94e8b4;hpb=e7498a3ee1d0484d02a9e86633cc179c76ebf36e;p=ghc-hetmet.git diff --git a/ghc/compiler/nativeGen/MachRegs.lhs b/ghc/compiler/nativeGen/MachRegs.lhs index 7493de4..bd72d6b 100644 --- a/ghc/compiler/nativeGen/MachRegs.lhs +++ b/ghc/compiler/nativeGen/MachRegs.lhs @@ -1,5 +1,5 @@ % -% (c) The AQUA Project, Glasgow University, 1996 +% (c) The AQUA Project, Glasgow University, 1996-1998 % \section[MachRegs]{Machine-specific info about registers} @@ -10,31 +10,29 @@ often/usually quite entangled with registers. modules --- the pleasure has been foregone.) \begin{code} -#include "HsVersions.h" #include "nativeGen/NCG.h" module MachRegs ( Reg(..), Imm(..), - Addr(..), + MachRegsAddr(..), RegLoc(..), - RegNo(..), + RegNo, addrOffset, argRegs, baseRegOffset, callClobberedRegs, callerSaves, - dblImmLit, extractMappedRegNos, + mappedRegNo, freeMappedRegs, freeReg, freeRegs, getNewRegNCG, magicIdRegMaybe, mkReg, realReg, - reservedRegs, saveLoc, spRel, stgReg, @@ -44,11 +42,11 @@ module MachRegs ( , allArgRegs , fits8Bits , fReg - , gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zero + , gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh #endif #if i386_TARGET_ARCH , eax, ebx, ecx, edx, esi, esp - , st0, st1, st2, st3, st4, st5, st6, st7 + , fake0, fake1, fake2, fake3, fake4, fake5 #endif #if sparc_TARGET_ARCH , allArgRegs @@ -59,22 +57,20 @@ module MachRegs ( #endif ) where -IMP_Ubiq(){-uitous-} +#include "HsVersions.h" import AbsCSyn ( MagicId(..) ) import AbsCUtils ( magicIdPrimRep ) -import Pretty ( ppStr, ppRational, ppShow ) +import CLabel ( CLabel ) import PrimOp ( PrimOp(..) ) import PrimRep ( PrimRep(..) ) import Stix ( sStLitLbl, StixTree(..), StixReg(..), - CodeSegment - ) + getUniqueNat, returnNat, thenNat, NatM ) import Unique ( mkPseudoUnique1, mkPseudoUnique2, mkPseudoUnique3, - Unique{-instance Ord3-} + Uniquable(..), Unique ) -import UniqSupply ( getUnique, returnUs, thenUs, UniqSM(..) ) -import Unpretty ( uppStr, Unpretty(..) ) -import Util ( panic ) +--import UniqSupply ( getUniqueUs, returnUs, thenUs, UniqSM ) +import Outputable \end{code} % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -84,26 +80,21 @@ data Imm = ImmInt Int | ImmInteger Integer -- Sigh. | ImmCLbl CLabel -- AbstractC Label (with baggage) - | ImmLab Unpretty -- Simple string label (underscore-able) - | ImmLit Unpretty -- Simple string + | ImmLab SDoc -- Simple string label (underscore-able) + | ImmLit SDoc -- Simple string + | ImmIndex CLabel Int + | ImmDouble Rational IF_ARCH_sparc( | LO Imm -- Possible restrictions... | HI Imm ,) - -strImmLit s = ImmLit (uppStr s) -dblImmLit r - = strImmLit ( - IF_ARCH_alpha({-prepend nothing-} - ,IF_ARCH_i386( '0' : 'd' : - ,IF_ARCH_sparc('0' : 'r' :,))) - ppShow 80 (ppRational r)) +strImmLit s = ImmLit (text s) \end{code} % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \begin{code} -data Addr +data MachRegsAddr #if alpha_TARGET_ARCH = AddrImm Imm | AddrReg Reg @@ -111,8 +102,8 @@ data Addr #endif #if i386_TARGET_ARCH - = Addr Base Index Displacement - | ImmAddr Imm Int + = AddrBaseIndex Base Index Displacement + | ImmAddr Imm Int type Base = Maybe Reg type Index = Maybe (Reg, Int) -- Int is 2, 4 or 8 @@ -124,7 +115,7 @@ type Displacement = Imm | AddrRegImm Reg Imm #endif -addrOffset :: Addr -> Int -> Maybe Addr +addrOffset :: MachRegsAddr -> Int -> Maybe MachRegsAddr addrOffset addr off = case addr of @@ -133,9 +124,9 @@ addrOffset addr off #endif #if i386_TARGET_ARCH ImmAddr i off0 -> Just (ImmAddr i (off0 + off)) - Addr r i (ImmInt n) -> Just (Addr r i (ImmInt (n + off))) - Addr r i (ImmInteger n) - -> Just (Addr r i (ImmInt (fromInteger (n + toInteger off)))) + AddrBaseIndex r i (ImmInt n) -> Just (AddrBaseIndex r i (ImmInt (n + off))) + AddrBaseIndex r i (ImmInteger n) + -> Just (AddrBaseIndex r i (ImmInt (fromInteger (n + toInteger off)))) _ -> Nothing #endif #if sparc_TARGET_ARCH @@ -216,21 +207,8 @@ stgReg x Nothing -> sStLitLbl SLIT("MainRegTable") nonReg = case x of - StkStubReg -> sStLitLbl SLIT("STK_STUB_closure") - StdUpdRetVecReg -> sStLitLbl SLIT("vtbl_StdUpdFrame") BaseReg -> sStLitLbl SLIT("MainRegTable") - -- these Hp&HpLim cases perhaps should - -- not be here for i386 (???) WDP 96/03 - Hp -> StInd PtrRep (sStLitLbl SLIT("StorageMgrInfo")) - HpLim -> StInd PtrRep (sStLitLbl - (_PK_ ("StorageMgrInfo+" ++ BYTES_PER_WORD_STR))) - TagReg -> StInd IntRep (StPrim IntSubOp [infoptr, - StInt (1*BYTES_PER_WORD)]) - where - r2 = VanillaReg PtrRep ILIT(2) - infoptr = case (stgReg r2) of - Always t -> t - Save _ -> StReg (StixMagicId r2) + _ -> StInd (magicIdPrimRep x) (StPrim IntAddOp [baseLoc, StInt (toInteger (offset*BYTES_PER_WORD))]) @@ -244,17 +222,17 @@ applicable, is the same but for the frame pointer. \begin{code} spRel :: Int -- desired stack offset in words, positive or negative - -> Addr + -> MachRegsAddr spRel n #if i386_TARGET_ARCH - = Addr (Just esp) Nothing (ImmInt (n * BYTES_PER_WORD)) + = AddrBaseIndex (Just esp) Nothing (ImmInt (n * BYTES_PER_WORD)) #else = AddrRegImm sp (ImmInt (n * BYTES_PER_WORD)) #endif #if sparc_TARGET_ARCH -fpRel :: Int -> Addr +fpRel :: Int -> MachRegsAddr -- Duznae work for offsets greater than 13 bits; we just hope for -- the best fpRel n @@ -290,16 +268,15 @@ data Reg | UnmappedReg Unique PrimRep -- One of an infinite supply of registers, -- always mapped to one of the earlier -- two (?) before we're done. - mkReg :: Unique -> PrimRep -> Reg mkReg = UnmappedReg -getNewRegNCG :: PrimRep -> UniqSM Reg +getNewRegNCG :: PrimRep -> NatM Reg getNewRegNCG pk - = getUnique `thenUs` \ u -> - returnUs (UnmappedReg u pk) + = getUniqueNat `thenNat` \ u -> + returnNat (UnmappedReg u pk) -instance Text Reg where +instance Show Reg where showsPrec _ (FixedReg i) = showString "%" . shows IBOX(i) showsPrec _ (MappedReg i) = showString "%" . shows IBOX(i) showsPrec _ (MemoryReg i _) = showString "%M" . shows i @@ -307,49 +284,43 @@ instance Text Reg where #ifdef DEBUG instance Outputable Reg where - ppr sty r = ppStr (show r) + ppr r = text (show r) #endif cmpReg (FixedReg i) (FixedReg i') = cmp_ihash i i' cmpReg (MappedReg i) (MappedReg i') = cmp_ihash i i' -cmpReg (MemoryReg i _) (MemoryReg i' _) = cmp_i i i' -cmpReg (UnmappedReg u _) (UnmappedReg u' _) = cmp u u' +cmpReg (MemoryReg i _) (MemoryReg i' _) = i `compare` i' +cmpReg (UnmappedReg u _) (UnmappedReg u' _) = compare u u' cmpReg r1 r2 = let tag1 = tagReg r1 tag2 = tagReg r2 in - if tag1 _LT_ tag2 then LT_ else GT_ + if tag1 _LT_ tag2 then LT else GT where tagReg (FixedReg _) = (ILIT(1) :: FAST_INT) tagReg (MappedReg _) = ILIT(2) tagReg (MemoryReg _ _) = ILIT(3) tagReg (UnmappedReg _ _) = ILIT(4) -cmp_i :: Int -> Int -> TAG_ -cmp_i a1 a2 = if a1 == a2 then EQ_ else if a1 < a2 then LT_ else GT_ - -cmp_ihash :: FAST_INT -> FAST_INT -> TAG_ -cmp_ihash a1 a2 = if a1 _EQ_ a2 then EQ_ else if a1 _LT_ a2 then LT_ else GT_ - -instance Ord3 Reg where - cmp = cmpReg +cmp_ihash :: FAST_INT -> FAST_INT -> Ordering +cmp_ihash a1 a2 = if a1 _EQ_ a2 then EQ else if a1 _LT_ a2 then LT else GT instance Eq Reg where - a == b = case (a `cmp` b) of { EQ_ -> True; _ -> False } - a /= b = case (a `cmp` b) of { EQ_ -> False; _ -> True } + a == b = case (a `compare` b) of { EQ -> True; _ -> False } + a /= b = case (a `compare` b) of { EQ -> False; _ -> True } instance Ord Reg where - a <= b = case (a `cmp` b) of { LT_ -> True; EQ_ -> True; GT__ -> False } - a < b = case (a `cmp` b) of { LT_ -> True; EQ_ -> False; GT__ -> False } - a >= b = case (a `cmp` b) of { LT_ -> False; EQ_ -> True; GT__ -> True } - a > b = case (a `cmp` b) of { LT_ -> False; EQ_ -> False; GT__ -> True } - _tagCmp a b = case (a `cmp` b) of { LT_ -> _LT; EQ_ -> _EQ; GT__ -> _GT } + a <= b = case (a `compare` b) of { LT -> True; EQ -> True; GT -> False } + a < b = case (a `compare` b) of { LT -> True; EQ -> False; GT -> False } + a >= b = case (a `compare` b) of { LT -> False; EQ -> True; GT -> True } + a > b = case (a `compare` b) of { LT -> False; EQ -> False; GT -> True } + compare a b = cmpReg a b instance Uniquable Reg where - uniqueOf (UnmappedReg u _) = u - uniqueOf (FixedReg i) = mkPseudoUnique1 IBOX(i) - uniqueOf (MappedReg i) = mkPseudoUnique2 IBOX(i) - uniqueOf (MemoryReg i _) = mkPseudoUnique3 i + getUnique (UnmappedReg u _) = u + getUnique (FixedReg i) = mkPseudoUnique1 IBOX(i) + getUnique (MappedReg i) = mkPseudoUnique2 IBOX(i) + getUnique (MemoryReg i _) = mkPseudoUnique3 i \end{code} \begin{code} @@ -366,6 +337,10 @@ extractMappedRegNos regs where ex (MappedReg i) acc = IBOX(i) : acc -- we'll take it ex _ acc = acc -- leave it out + +mappedRegNo :: Reg -> RegNo +mappedRegNo (MappedReg i) = IBOX(i) +mappedRegNo _ = pprPanic "mappedRegNo" empty \end{code} ** Machine-specific Reg stuff: ** @@ -378,14 +353,14 @@ is defined in StgRegs.h. We are, of course, prepared for any eventuality. fReg :: Int -> Int fReg x = (32 + x) -v0, f0, ra, pv, gp, sp, zero :: Reg -v0 = realReg 0 -f0 = realReg (fReg 0) -ra = FixedReg ILIT(26) -pv = t12 -gp = FixedReg ILIT(29) -sp = FixedReg ILIT(30) -zero = FixedReg ILIT(31) +v0, f0, ra, pv, gp, sp, zeroh :: Reg +v0 = realReg 0 +f0 = realReg (fReg 0) +ra = FixedReg ILIT(26) +pv = t12 +gp = FixedReg ILIT(29) +sp = FixedReg ILIT(30) +zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method) t9, t10, t11, t12 :: Reg t9 = realReg 23 @@ -400,7 +375,10 @@ Intel x86 architecture: - Only ebx, esi, edi and esp are available across a C call (they are callee-saves). - Registers 0-7 have 16-bit counterparts (ax, bx etc.) - Registers 0-3 have 8 bit counterparts (ah, bh etc.) -- Registers 8-15 hold extended floating point values. +- Registers 8-13 are fakes; we pretend x86 has 6 conventionally-addressable + fp registers, and 3-operand insns for them, and we translate this into + real stack-based x86 fp code after register allocation. + \begin{code} #if i386_TARGET_ARCH @@ -408,24 +386,21 @@ gReg,fReg :: Int -> Int gReg x = x fReg x = (8 + x) -st0, st1, st2, st3, st4, st5, st6, st7, eax, ebx, ecx, edx, esp :: Reg -eax = case (gReg 0) of { IBOX(g0) -> FixedReg g0 } -ebx = case (gReg 1) of { IBOX(g1) -> FixedReg g1 } -ecx = case (gReg 2) of { IBOX(g2) -> FixedReg g2 } -edx = case (gReg 3) of { IBOX(g3) -> FixedReg g3 } -esi = case (gReg 4) of { IBOX(g4) -> FixedReg g4 } -edi = case (gReg 5) of { IBOX(g5) -> FixedReg g5 } -ebp = case (gReg 6) of { IBOX(g6) -> FixedReg g6 } -esp = case (gReg 7) of { IBOX(g7) -> FixedReg g7 } -st0 = realReg (fReg 0) -st1 = realReg (fReg 1) -st2 = realReg (fReg 2) -st3 = realReg (fReg 3) -st4 = realReg (fReg 4) -st5 = realReg (fReg 5) -st6 = realReg (fReg 6) -st7 = realReg (fReg 7) - +fake0, fake1, fake2, fake3, fake4, fake5, eax, ebx, ecx, edx, esp :: Reg +eax = realReg (gReg 0) +ebx = realReg (gReg 1) +ecx = realReg (gReg 2) +edx = realReg (gReg 3) +esi = realReg (gReg 4) +edi = realReg (gReg 5) +ebp = realReg (gReg 6) +esp = realReg (gReg 7) +fake0 = realReg (fReg 0) +fake1 = realReg (fReg 1) +fake2 = realReg (fReg 2) +fake3 = realReg (fReg 3) +fake4 = realReg (fReg 4) +fake5 = realReg (fReg 5) #endif \end{code} @@ -504,14 +479,12 @@ names in the header files. Gag me with a spoon, eh? #define edi 5 #define ebp 6 #define esp 7 -#define st0 8 -#define st1 9 -#define st2 10 -#define st3 11 -#define st4 12 -#define st5 13 -#define st6 14 -#define st7 15 +#define fake0 8 +#define fake1 9 +#define fake2 10 +#define fake3 11 +#define fake4 12 +#define fake5 13 #endif #if sparc_TARGET_ARCH #define g0 0 @@ -584,7 +557,6 @@ names in the header files. Gag me with a spoon, eh? \begin{code} baseRegOffset :: MagicId -> Int -baseRegOffset StkOReg = OFFSET_StkO baseRegOffset (VanillaReg _ ILIT(1)) = OFFSET_R1 baseRegOffset (VanillaReg _ ILIT(2)) = OFFSET_R2 baseRegOffset (VanillaReg _ ILIT(3)) = OFFSET_R3 @@ -593,25 +565,27 @@ baseRegOffset (VanillaReg _ ILIT(5)) = OFFSET_R5 baseRegOffset (VanillaReg _ ILIT(6)) = OFFSET_R6 baseRegOffset (VanillaReg _ ILIT(7)) = OFFSET_R7 baseRegOffset (VanillaReg _ ILIT(8)) = OFFSET_R8 -baseRegOffset (FloatReg ILIT(1)) = OFFSET_Flt1 -baseRegOffset (FloatReg ILIT(2)) = OFFSET_Flt2 -baseRegOffset (FloatReg ILIT(3)) = OFFSET_Flt3 -baseRegOffset (FloatReg ILIT(4)) = OFFSET_Flt4 -baseRegOffset (DoubleReg ILIT(1)) = OFFSET_Dbl1 -baseRegOffset (DoubleReg ILIT(2)) = OFFSET_Dbl2 -baseRegOffset TagReg = OFFSET_Tag -baseRegOffset RetReg = OFFSET_Ret -baseRegOffset SpA = OFFSET_SpA -baseRegOffset SuA = OFFSET_SuA -baseRegOffset SpB = OFFSET_SpB -baseRegOffset SuB = OFFSET_SuB +baseRegOffset (VanillaReg _ ILIT(9)) = OFFSET_R9 +baseRegOffset (VanillaReg _ ILIT(10)) = OFFSET_R10 +baseRegOffset (FloatReg ILIT(1)) = OFFSET_F1 +baseRegOffset (FloatReg ILIT(2)) = OFFSET_F2 +baseRegOffset (FloatReg ILIT(3)) = OFFSET_F3 +baseRegOffset (FloatReg ILIT(4)) = OFFSET_F4 +baseRegOffset (DoubleReg ILIT(1)) = OFFSET_D1 +baseRegOffset (DoubleReg ILIT(2)) = OFFSET_D2 +baseRegOffset Sp = OFFSET_Sp +baseRegOffset Su = OFFSET_Su +baseRegOffset SpLim = OFFSET_SpLim +#ifdef OFFSET_Lng1 +baseRegOffset (LongReg _ ILIT(1)) = OFFSET_Lng1 +#endif +#ifdef OFFSET_Lng2 +baseRegOffset (LongReg _ ILIT(2)) = OFFSET_Lng2 +#endif baseRegOffset Hp = OFFSET_Hp baseRegOffset HpLim = OFFSET_HpLim -baseRegOffset LivenessReg = OFFSET_Liveness #ifdef DEBUG baseRegOffset BaseReg = panic "baseRegOffset:BaseReg" -baseRegOffset StdUpdRetVecReg = panic "baseRegOffset:StgUpdRetVecReg" -baseRegOffset StkStubReg = panic "baseRegOffset:StkStubReg" baseRegOffset CurCostCentre = panic "baseRegOffset:CurCostCentre" baseRegOffset VoidReg = panic "baseRegOffset:VoidReg" #endif @@ -623,9 +597,6 @@ callerSaves :: MagicId -> Bool #ifdef CALLER_SAVES_Base callerSaves BaseReg = True #endif -#ifdef CALLER_SAVES_StkO -callerSaves StkOReg = True -#endif #ifdef CALLER_SAVES_R1 callerSaves (VanillaReg _ ILIT(1)) = True #endif @@ -650,41 +621,35 @@ callerSaves (VanillaReg _ ILIT(7)) = True #ifdef CALLER_SAVES_R8 callerSaves (VanillaReg _ ILIT(8)) = True #endif -#ifdef CALLER_SAVES_FltReg1 +#ifdef CALLER_SAVES_F1 callerSaves (FloatReg ILIT(1)) = True #endif -#ifdef CALLER_SAVES_FltReg2 +#ifdef CALLER_SAVES_F2 callerSaves (FloatReg ILIT(2)) = True #endif -#ifdef CALLER_SAVES_FltReg3 +#ifdef CALLER_SAVES_F3 callerSaves (FloatReg ILIT(3)) = True #endif -#ifdef CALLER_SAVES_FltReg4 +#ifdef CALLER_SAVES_F4 callerSaves (FloatReg ILIT(4)) = True #endif -#ifdef CALLER_SAVES_DblReg1 +#ifdef CALLER_SAVES_D1 callerSaves (DoubleReg ILIT(1)) = True #endif -#ifdef CALLER_SAVES_DblReg2 +#ifdef CALLER_SAVES_D2 callerSaves (DoubleReg ILIT(2)) = True #endif -#ifdef CALLER_SAVES_Tag -callerSaves TagReg = True -#endif -#ifdef CALLER_SAVES_Ret -callerSaves RetReg = True -#endif -#ifdef CALLER_SAVES_SpA -callerSaves SpA = True +#ifdef CALLER_SAVES_L1 +callerSaves (LongReg _ ILIT(1)) = True #endif -#ifdef CALLER_SAVES_SuA -callerSaves SuA = True +#ifdef CALLER_SAVES_Sp +callerSaves Sp = True #endif -#ifdef CALLER_SAVES_SpB -callerSaves SpB = True +#ifdef CALLER_SAVES_Su +callerSaves Su = True #endif -#ifdef CALLER_SAVES_SuB -callerSaves SuB = True +#ifdef CALLER_SAVES_SpLim +callerSaves SpLim = True #endif #ifdef CALLER_SAVES_Hp callerSaves Hp = True @@ -692,15 +657,6 @@ callerSaves Hp = True #ifdef CALLER_SAVES_HpLim callerSaves HpLim = True #endif -#ifdef CALLER_SAVES_Liveness -callerSaves LivenessReg = True -#endif -#ifdef CALLER_SAVES_StdUpdRetVec -callerSaves StdUpdRetVecReg = True -#endif -#ifdef CALLER_SAVES_StkStub -callerSaves StkStubReg = True -#endif callerSaves _ = False \end{code} @@ -710,9 +666,6 @@ magicIdRegMaybe :: MagicId -> Maybe Reg #ifdef REG_Base magicIdRegMaybe BaseReg = Just (FixedReg ILIT(REG_Base)) #endif -#ifdef REG_StkO -magicIdRegMaybe StkOReg = Just (FixedReg ILIT(REG_StkOReg)) -#endif #ifdef REG_R1 magicIdRegMaybe (VanillaReg _ ILIT(1)) = Just (FixedReg ILIT(REG_R1)) #endif @@ -737,41 +690,44 @@ magicIdRegMaybe (VanillaReg _ ILIT(7)) = Just (FixedReg ILIT(REG_R7)) #ifdef REG_R8 magicIdRegMaybe (VanillaReg _ ILIT(8)) = Just (FixedReg ILIT(REG_R8)) #endif -#ifdef REG_Flt1 -magicIdRegMaybe (FloatReg ILIT(1)) = Just (FixedReg ILIT(REG_Flt1)) +#ifdef REG_R9 +magicIdRegMaybe (VanillaReg _ ILIT(9)) = Just (FixedReg ILIT(REG_R9)) +#endif +#ifdef REG_R10 +magicIdRegMaybe (VanillaReg _ ILIT(10)) = Just (FixedReg ILIT(REG_R10)) +#endif +#ifdef REG_F1 +magicIdRegMaybe (FloatReg ILIT(1)) = Just (FixedReg ILIT(REG_F1)) #endif -#ifdef REG_Flt2 -magicIdRegMaybe (FloatReg ILIT(2)) = Just (FixedReg ILIT(REG_Flt2)) +#ifdef REG_F2 +magicIdRegMaybe (FloatReg ILIT(2)) = Just (FixedReg ILIT(REG_F2)) #endif -#ifdef REG_Flt3 -magicIdRegMaybe (FloatReg ILIT(3)) = Just (FixedReg ILIT(REG_Flt3)) +#ifdef REG_F3 +magicIdRegMaybe (FloatReg ILIT(3)) = Just (FixedReg ILIT(REG_F3)) #endif -#ifdef REG_Flt4 -magicIdRegMaybe (FloatReg ILIT(4)) = Just (FixedReg ILIT(REG_Flt4)) +#ifdef REG_F4 +magicIdRegMaybe (FloatReg ILIT(4)) = Just (FixedReg ILIT(REG_F4)) #endif -#ifdef REG_Dbl1 -magicIdRegMaybe (DoubleReg ILIT(1)) = Just (FixedReg ILIT(REG_Dbl1)) +#ifdef REG_D1 +magicIdRegMaybe (DoubleReg ILIT(1)) = Just (FixedReg ILIT(REG_D1)) #endif -#ifdef REG_Dbl2 -magicIdRegMaybe (DoubleReg ILIT(2)) = Just (FixedReg ILIT(REG_Dbl2)) -#endif -#ifdef REG_Tag -magicIdRegMaybe TagReg = Just (FixedReg ILIT(REG_TagReg)) -#endif -#ifdef REG_Ret -magicIdRegMaybe RetReg = Just (FixedReg ILIT(REG_Ret)) -#endif -#ifdef REG_SpA -magicIdRegMaybe SpA = Just (FixedReg ILIT(REG_SpA)) -#endif -#ifdef REG_SuA -magicIdRegMaybe SuA = Just (FixedReg ILIT(REG_SuA)) -#endif -#ifdef REG_SpB -magicIdRegMaybe SpB = Just (FixedReg ILIT(REG_SpB)) +#ifdef REG_D2 +magicIdRegMaybe (DoubleReg ILIT(2)) = Just (FixedReg ILIT(REG_D2)) +#endif +#ifdef REG_Sp +magicIdRegMaybe Sp = Just (FixedReg ILIT(REG_Sp)) +#endif +#ifdef REG_Lng1 +magicIdRegMaybe (LongReg _ ILIT(1)) = Just (FixedReg ILIT(REG_Lng1)) +#endif +#ifdef REG_Lng2 +magicIdRegMaybe (LongReg _ ILIT(2)) = Just (FixedReg ILIT(REG_Lng2)) +#endif +#ifdef REG_Su +magicIdRegMaybe Su = Just (FixedReg ILIT(REG_Su)) #endif -#ifdef REG_SuB -magicIdRegMaybe SuB = Just (FixedReg ILIT(REG_SuB)) +#ifdef REG_SpLim +magicIdRegMaybe SpLim = Just (FixedReg ILIT(REG_SpLim)) #endif #ifdef REG_Hp magicIdRegMaybe Hp = Just (FixedReg ILIT(REG_Hp)) @@ -779,57 +735,15 @@ magicIdRegMaybe Hp = Just (FixedReg ILIT(REG_Hp)) #ifdef REG_HpLim magicIdRegMaybe HpLim = Just (FixedReg ILIT(REG_HpLim)) #endif -#ifdef REG_Liveness -magicIdRegMaybe LivenessReg = Just (FixedReg ILIT(REG_Liveness)) -#endif -#ifdef REG_StdUpdRetVec -magicIdRegMaybe StdUpdRetVecReg = Just (FixedReg ILIT(REG_StdUpdRetVec)) -#endif -#ifdef REG_StkStub -magicIdRegMaybe StkStubReg = Just (FixedReg ILIT(REG_StkStub)) -#endif magicIdRegMaybe _ = Nothing \end{code} -%************************************************************************ -%* * -\subsection{Free, reserved, call-clobbered, and argument registers} -%* * -%************************************************************************ - -@freeRegs@ is the list of registers we can use in register allocation. -@freeReg@ (below) says if a particular register is free. - -With a per-instruction clobber list, we might be able to get some of -these back, but it's probably not worth the hassle. - -@callClobberedRegs@ ... the obvious. - -@argRegs@: assuming a call with N arguments, what registers will be -used to hold arguments? (NB: it doesn't know whether the arguments -are integer or floating-point...) - \begin{code} -reservedRegs :: [RegNo] -reservedRegs -#if alpha_TARGET_ARCH - = [NCG_Reserved_I1, NCG_Reserved_I2, - NCG_Reserved_F1, NCG_Reserved_F2] -#endif -#if i386_TARGET_ARCH - = [{-certainly cannot afford any!-}] -#endif -#if sparc_TARGET_ARCH - = [NCG_Reserved_I1, NCG_Reserved_I2, - NCG_Reserved_F1, NCG_Reserved_F2, - NCG_Reserved_D1, NCG_Reserved_D2] -#endif - ------------------------------- freeRegs :: [Reg] freeRegs = freeMappedRegs IF_ARCH_alpha( [0..63], - IF_ARCH_i386( [0..15], + IF_ARCH_i386( [0..13], IF_ARCH_sparc( [0..63],))) ------------------------------- @@ -857,6 +771,9 @@ callClobberedRegs argRegs :: Int -> [Reg] argRegs 0 = [] +#if i386_TARGET_ARCH +argRegs _ = panic "MachRegs.argRegs: doesn't work on I386" +#else #if alpha_TARGET_ARCH argRegs 1 = freeMappedRegs [16, fReg 16] argRegs 2 = freeMappedRegs [16, 17, fReg 16, fReg 17] @@ -865,9 +782,6 @@ argRegs 4 = freeMappedRegs [16, 17, 18, 19, fReg 16, fReg 17, fReg 18, fReg 19] argRegs 5 = freeMappedRegs [16, 17, 18, 19, 20, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20] argRegs 6 = freeMappedRegs [16, 17, 18, 19, 20, 21, fReg 16, fReg 17, fReg 18, fReg 19, fReg 20, fReg 21] #endif {- alpha_TARGET_ARCH -} -#if i386_TARGET_ARCH -argRegs _ = panic "MachRegs.argRegs: doesn't work on I386" -#endif {- i386_TARGET_ARCH -} #if sparc_TARGET_ARCH argRegs 1 = freeMappedRegs (map oReg [0]) argRegs 2 = freeMappedRegs (map oReg [0,1]) @@ -877,6 +791,7 @@ argRegs 5 = freeMappedRegs (map oReg [0,1,2,3,4]) argRegs 6 = freeMappedRegs (map oReg [0,1,2,3,4,5]) #endif {- sparc_TARGET_ARCH -} argRegs _ = panic "MachRegs.argRegs: don't know about >6 arguments!" +#endif {- i386_TARGET_ARCH -} ------------------------------- @@ -910,7 +825,7 @@ freeReg ILIT(26) = _FALSE_ -- return address (ra) freeReg ILIT(28) = _FALSE_ -- reserved for the assembler (at) freeReg ILIT(29) = _FALSE_ -- global pointer (gp) freeReg ILIT(30) = _FALSE_ -- stack pointer (sp) -freeReg ILIT(31) = _FALSE_ -- always zero (zero) +freeReg ILIT(31) = _FALSE_ -- always zero (zeroh) freeReg ILIT(63) = _FALSE_ -- always zero (f31) #endif @@ -930,9 +845,6 @@ freeReg ILIT(o6) = _FALSE_ -- %o6 is our stack pointer. #ifdef REG_Base freeReg ILIT(REG_Base) = _FALSE_ #endif -#ifdef REG_StkO -freeReg ILIT(REG_StkO) = _FALSE_ -#endif #ifdef REG_R1 freeReg ILIT(REG_R1) = _FALSE_ #endif @@ -957,41 +869,32 @@ freeReg ILIT(REG_R7) = _FALSE_ #ifdef REG_R8 freeReg ILIT(REG_R8) = _FALSE_ #endif -#ifdef REG_Flt1 -freeReg ILIT(REG_Flt1) = _FALSE_ +#ifdef REG_F1 +freeReg ILIT(REG_F1) = _FALSE_ #endif -#ifdef REG_Flt2 -freeReg ILIT(REG_Flt2) = _FALSE_ +#ifdef REG_F2 +freeReg ILIT(REG_F2) = _FALSE_ #endif -#ifdef REG_Flt3 -freeReg ILIT(REG_Flt3) = _FALSE_ +#ifdef REG_F3 +freeReg ILIT(REG_F3) = _FALSE_ #endif -#ifdef REG_Flt4 -freeReg ILIT(REG_Flt4) = _FALSE_ +#ifdef REG_F4 +freeReg ILIT(REG_F4) = _FALSE_ #endif -#ifdef REG_Dbl1 -freeReg ILIT(REG_Dbl1) = _FALSE_ +#ifdef REG_D1 +freeReg ILIT(REG_D1) = _FALSE_ #endif -#ifdef REG_Dbl2 -freeReg ILIT(REG_Dbl2) = _FALSE_ +#ifdef REG_D2 +freeReg ILIT(REG_D2) = _FALSE_ #endif -#ifdef REG_Tag -freeReg ILIT(REG_Tag) = _FALSE_ -#endif -#ifdef REG_Ret -freeReg ILIT(REG_Ret) = _FALSE_ -#endif -#ifdef REG_SpA -freeReg ILIT(REG_SpA) = _FALSE_ -#endif -#ifdef REG_SuA -freeReg ILIT(REG_SuA) = _FALSE_ +#ifdef REG_Sp +freeReg ILIT(REG_Sp) = _FALSE_ #endif -#ifdef REG_SpB -freeReg ILIT(REG_SpB) = _FALSE_ +#ifdef REG_Su +freeReg ILIT(REG_Su) = _FALSE_ #endif -#ifdef REG_SuB -freeReg ILIT(REG_SuB) = _FALSE_ +#ifdef REG_SpLim +freeReg ILIT(REG_SpLim) = _FALSE_ #endif #ifdef REG_Hp freeReg ILIT(REG_Hp) = _FALSE_ @@ -999,25 +902,15 @@ freeReg ILIT(REG_Hp) = _FALSE_ #ifdef REG_HpLim freeReg ILIT(REG_HpLim) = _FALSE_ #endif -#ifdef REG_Liveness -freeReg ILIT(REG_Liveness) = _FALSE_ -#endif -#ifdef REG_StdUpdRetVec -freeReg ILIT(REG_StdUpdRetVec) = _FALSE_ -#endif -#ifdef REG_StkStub -freeReg ILIT(REG_StkStub) = _FALSE_ -#endif -freeReg _ = _TRUE_ freeReg n -- we hang onto two double regs for dedicated -- use; this is not necessary on Alphas and -- may not be on other non-SPARCs. -#ifdef REG_Dbl1 - | n _EQ_ (ILIT(REG_Dbl1) _ADD_ ILIT(1)) = _FALSE_ +#ifdef REG_D1 + | n _EQ_ (ILIT(REG_D1) _ADD_ ILIT(1)) = _FALSE_ #endif -#ifdef REG_Dbl2 - | n _EQ_ (ILIT(REG_Dbl2) _ADD_ ILIT(1)) = _FALSE_ +#ifdef REG_D2 + | n _EQ_ (ILIT(REG_D2) _ADD_ ILIT(1)) = _FALSE_ #endif | otherwise = _TRUE_ \end{code}