X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=ghc%2Fcompiler%2FnativeGen%2FMachRegs.lhs;h=db21aaa28a40a56e5b32b7ff4a5bfd45c336c7ce;hb=fda89b29c748c6cd2fe1fdb477d5c0e8f7d32b90;hp=b48f136dc55170104f65a1c889316c29ae50d560;hpb=26741ec416bae2c502ef00a2ba0e79050a32cb67;p=ghc-hetmet.git diff --git a/ghc/compiler/nativeGen/MachRegs.lhs b/ghc/compiler/nativeGen/MachRegs.lhs index b48f136..db21aaa 100644 --- a/ghc/compiler/nativeGen/MachRegs.lhs +++ b/ghc/compiler/nativeGen/MachRegs.lhs @@ -19,7 +19,7 @@ module MachRegs ( Imm(..), Addr(..), RegLoc(..), - RegNo(..), + SYN_IE(RegNo), addrOffset, argRegs, @@ -44,7 +44,7 @@ module MachRegs ( , allArgRegs , fits8Bits , fReg - , gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zero + , gp, pv, ra, sp, t9, t10, t11, t12, v0, f0, zeroh #endif #if i386_TARGET_ARCH , eax, ebx, ecx, edx, esi, esp @@ -59,22 +59,28 @@ module MachRegs ( #endif ) where +#if __GLASGOW_HASKELL__ >= 202 +import GlaExts hiding (Addr) +import FastString +#else IMP_Ubiq(){-uitous-} +#endif import AbsCSyn ( MagicId(..) ) import AbsCUtils ( magicIdPrimRep ) -import Pretty ( ppStr, ppRational, ppShow ) +import CLabel ( CLabel ) +import Outputable ( Outputable(..) ) +import Pretty ( Doc, text, rational ) import PrimOp ( PrimOp(..) ) import PrimRep ( PrimRep(..) ) import Stix ( sStLitLbl, StixTree(..), StixReg(..), CodeSegment ) import Unique ( mkPseudoUnique1, mkPseudoUnique2, mkPseudoUnique3, - Unique{-instance Ord3-} + Unique{-instance Ord3-}, Uniquable(..) ) import UniqSupply ( getUnique, returnUs, thenUs, SYN_IE(UniqSM) ) -import Unpretty ( uppStr, Unpretty(..) ) -import Util ( panic ) +import Util ( panic, Ord3(..) ) \end{code} % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -84,20 +90,19 @@ data Imm = ImmInt Int | ImmInteger Integer -- Sigh. | ImmCLbl CLabel -- AbstractC Label (with baggage) - | ImmLab Unpretty -- Simple string label (underscore-able) - | ImmLit Unpretty -- Simple string + | ImmLab Doc -- Simple string label (underscore-able) + | ImmLit Doc -- Simple string IF_ARCH_sparc( | LO Imm -- Possible restrictions... | HI Imm ,) - -strImmLit s = ImmLit (uppStr s) +strImmLit s = ImmLit (text s) dblImmLit r = strImmLit ( IF_ARCH_alpha({-prepend nothing-} ,IF_ARCH_i386( '0' : 'd' : ,IF_ARCH_sparc('0' : 'r' :,))) - ppShow 80 (ppRational r)) + show (rational r)) \end{code} % - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -290,7 +295,6 @@ data Reg | UnmappedReg Unique PrimRep -- One of an infinite supply of registers, -- always mapped to one of the earlier -- two (?) before we're done. - mkReg :: Unique -> PrimRep -> Reg mkReg = UnmappedReg @@ -307,7 +311,7 @@ instance Text Reg where #ifdef DEBUG instance Outputable Reg where - ppr sty r = ppStr (show r) + ppr sty r = text (show r) #endif cmpReg (FixedReg i) (FixedReg i') = cmp_ihash i i' @@ -378,14 +382,14 @@ is defined in StgRegs.h. We are, of course, prepared for any eventuality. fReg :: Int -> Int fReg x = (32 + x) -v0, f0, ra, pv, gp, sp, zero :: Reg -v0 = realReg 0 -f0 = realReg (fReg 0) -ra = FixedReg ILIT(26) -pv = t12 -gp = FixedReg ILIT(29) -sp = FixedReg ILIT(30) -zero = FixedReg ILIT(31) +v0, f0, ra, pv, gp, sp, zeroh :: Reg +v0 = realReg 0 +f0 = realReg (fReg 0) +ra = FixedReg ILIT(26) +pv = t12 +gp = FixedReg ILIT(29) +sp = FixedReg ILIT(30) +zeroh = FixedReg ILIT(31) -- "zero" is used in 1.3 (MonadZero method) t9, t10, t11, t12 :: Reg t9 = realReg 23 @@ -910,7 +914,7 @@ freeReg ILIT(26) = _FALSE_ -- return address (ra) freeReg ILIT(28) = _FALSE_ -- reserved for the assembler (at) freeReg ILIT(29) = _FALSE_ -- global pointer (gp) freeReg ILIT(30) = _FALSE_ -- stack pointer (sp) -freeReg ILIT(31) = _FALSE_ -- always zero (zero) +freeReg ILIT(31) = _FALSE_ -- always zero (zeroh) freeReg ILIT(63) = _FALSE_ -- always zero (f31) #endif