X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=ghc%2Fcompiler%2FnativeGen%2FRegAllocInfo.lhs;h=e0377b801f43afda9114d83ffd914a9be3aa241d;hb=56af76cc6a264621bfd18071f21e6a608e691e47;hp=56f43561cf035218e04f7b099c8366947f94c9a2;hpb=b08b5149482e9d88b3a0f5098e7b118e6f00e115;p=ghc-hetmet.git

diff --git a/ghc/compiler/nativeGen/RegAllocInfo.lhs b/ghc/compiler/nativeGen/RegAllocInfo.lhs
index 56f4356..e0377b8 100644
--- a/ghc/compiler/nativeGen/RegAllocInfo.lhs
+++ b/ghc/compiler/nativeGen/RegAllocInfo.lhs
@@ -917,23 +917,23 @@ spillReg vreg_to_slot_map delta dyn vreg
 
 	{-I386: spill above stack pointer leaving 3 words/spill-}
 	,IF_ARCH_i386 ( let off_w = (off-delta) `div` 4
-                        in case regClass vreg of
-                              RcInteger -> MOV L (OpReg dyn) (OpAddr (spRel off_w))
-                              _         -> GST F80 dyn (spRel off_w) -- RcFloat/RcDouble
+                        in case regClass vreg of {
+                              RcInteger -> MOV L (OpReg dyn) (OpAddr (spRel off_w));
+                              _         -> GST F80 dyn (spRel off_w)} {- RcFloat/RcDouble -}
 
 	{-SPARC: spill below frame pointer leaving 2 words/spill-}
 	,IF_ARCH_sparc( 
-                        let off_w = 1 + (off `div` 4)
-                            sz = case regClass vreg of
-                                    RcInteger -> W
-                                    RcFloat   -> F
-                                    RcDouble  -> DF
+                        let{off_w = 1 + (off `div` 4);
+                            sz = case regClass vreg of {
+                                    RcInteger -> W;
+                                    RcFloat   -> F;
+                                    RcDouble  -> DF}}
                         in ST sz dyn (fpRel (- off_w))
         ,IF_ARCH_powerpc(
-			let sz = case regClass vreg of
-                                    RcInteger -> W
-                                    RcFloat   -> F
-                                    RcDouble  -> DF
+			let{sz = case regClass vreg of {
+                                    RcInteger -> W;
+                                    RcFloat   -> F;
+                                    RcDouble  -> DF}}
 			in ST sz dyn (AddrRegImm sp (ImmInt (off-delta)))
 	,))))
 
@@ -946,22 +946,22 @@ loadReg vreg_to_slot_map delta vreg dyn
 	 IF_ARCH_alpha( LD  sz dyn (spRel (- (off `div` 8)))
 
 	,IF_ARCH_i386 ( let off_w = (off-delta) `div` 4
-                        in case regClass vreg of
-                              RcInteger -> MOV L (OpAddr (spRel off_w)) (OpReg dyn)
-                              _         -> GLD F80 (spRel off_w) dyn -- RcFloat/RcDouble
+                        in case regClass vreg of {
+                              RcInteger -> MOV L (OpAddr (spRel off_w)) (OpReg dyn);
+                              _         -> GLD F80 (spRel off_w) dyn} {- RcFloat/RcDouble -}
 
 	,IF_ARCH_sparc( 
-                        let off_w = 1 + (off `div` 4)
-                            sz = case regClass vreg of
-                                   RcInteger -> W
-                                   RcFloat   -> F
-                                   RcDouble  -> DF
+                        let{off_w = 1 + (off `div` 4);
+                            sz = case regClass vreg of {
+                                   RcInteger -> W;
+                                   RcFloat   -> F;
+                                   RcDouble  -> DF}}
                         in LD sz (fpRel (- off_w)) dyn
         ,IF_ARCH_powerpc(
-			let sz = case regClass vreg of
-                                    RcInteger -> W
-                                    RcFloat   -> F
-                                    RcDouble  -> DF
+			let{sz = case regClass vreg of {
+                                    RcInteger -> W;
+                                    RcFloat   -> F;
+                                    RcDouble  -> DF}}
 			in LD sz dyn (AddrRegImm sp (ImmInt (off-delta)))
 	,))))
 \end{code}