X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=ghc%2Fcompiler%2FnativeGen%2FRegAllocInfo.lhs;h=e0377b801f43afda9114d83ffd914a9be3aa241d;hb=56af76cc6a264621bfd18071f21e6a608e691e47;hp=eaa1a1b4a75fd7e5ad09e157a1f86f184fb8e205;hpb=97906cfcc30dd591e840921d336fdabeb1b8a315;p=ghc-hetmet.git diff --git a/ghc/compiler/nativeGen/RegAllocInfo.lhs b/ghc/compiler/nativeGen/RegAllocInfo.lhs index eaa1a1b..e0377b8 100644 --- a/ghc/compiler/nativeGen/RegAllocInfo.lhs +++ b/ghc/compiler/nativeGen/RegAllocInfo.lhs @@ -121,7 +121,7 @@ intersectionRegSets (MkRegSet xs1) (MkRegSet xs2) %************************************************************************ %* * -\subsection{@RegUsage@ type; @noUsage@, @endUsage@, @regUsage@ functions} +\subsection{@RegUsage@ type; @noUsage@ and @regUsage@ functions} %* * %************************************************************************ @@ -398,27 +398,32 @@ regUsage instr = case instr of MR reg1 reg2 -> usage ([reg2], [reg1]) CMP sz reg ri -> usage (reg : regRI ri,[]) CMPL sz reg ri -> usage (reg : regRI ri,[]) + BCC cond lbl -> noUsage MTCTR reg -> usage ([reg],[]) + BCTR dsts -> noUsage + BL imm params -> usage (params, callClobberedRegs) + BCTRL params -> usage (params, callClobberedRegs) ADD reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1]) - SUBF reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1]) + SUBF reg1 reg2 reg3-> usage ([reg2,reg3], [reg1]) MULLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1]) DIVW reg1 reg2 reg3-> usage ([reg2,reg3], [reg1]) DIVWU reg1 reg2 reg3-> usage ([reg2,reg3], [reg1]) AND reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1]) OR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1]) XOR reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1]) + XORIS reg1 reg2 imm -> usage ([reg2], [reg1]) + NEG reg1 reg2 -> usage ([reg2], [reg1]) + NOT reg1 reg2 -> usage ([reg2], [reg1]) SLW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1]) SRW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1]) SRAW reg1 reg2 ri -> usage (reg2 : regRI ri, [reg1]) - NEG reg1 reg2 -> usage ([reg2], [reg1]) - NOT reg1 reg2 -> usage ([reg2], [reg1]) - BL imm params -> usage (params, callClobberedRegs) - BCTRL params -> usage (params, callClobberedRegs) FADD sz r1 r2 r3 -> usage ([r2,r3], [r1]) FSUB sz r1 r2 r3 -> usage ([r2,r3], [r1]) FMUL sz r1 r2 r3 -> usage ([r2,r3], [r1]) FDIV sz r1 r2 r3 -> usage ([r2,r3], [r1]) + FNEG r1 r2 -> usage ([r2], [r1]) FCMP r1 r2 -> usage ([r1,r2], []) + FCTIWZ r1 r2 -> usage ([r2], [r1]) _ -> noUsage where usage (src, dst) = RU (regSetFromList (filter interesting src)) @@ -606,7 +611,8 @@ insnFuture insn BCC _ clbl | isAsmTemp clbl -> NextOrBranch clbl BCC _ _ -> panic "insnFuture: conditional jump to non-local label" - BCTR -> NoFuture + BCTR (DestInfo dsts) -> MultiFuture dsts + BCTR NoDestInfo -> NoFuture boring -> Next #endif {- powerpc_TARGET_ARCH -} \end{code} @@ -828,25 +834,30 @@ patchRegs instr env = case instr of CMPL sz reg ri -> CMPL sz (env reg) (fixRI ri) BCC cond lbl -> BCC cond lbl MTCTR reg -> MTCTR (env reg) - BCTR -> BCTR + BCTR dsts -> BCTR dsts + BL imm argRegs -> BL imm argRegs -- argument regs + BCTRL argRegs -> BCTRL argRegs -- cannot be remapped ADD reg1 reg2 ri -> ADD (env reg1) (env reg2) (fixRI ri) - SUBF reg1 reg2 ri -> SUBF (env reg1) (env reg2) (fixRI ri) + SUBF reg1 reg2 reg3-> SUBF (env reg1) (env reg2) (env reg3) MULLW reg1 reg2 ri -> MULLW (env reg1) (env reg2) (fixRI ri) DIVW reg1 reg2 reg3-> DIVW (env reg1) (env reg2) (env reg3) DIVWU reg1 reg2 reg3-> DIVWU (env reg1) (env reg2) (env reg3) AND reg1 reg2 ri -> AND (env reg1) (env reg2) (fixRI ri) OR reg1 reg2 ri -> OR (env reg1) (env reg2) (fixRI ri) XOR reg1 reg2 ri -> XOR (env reg1) (env reg2) (fixRI ri) + XORIS reg1 reg2 imm -> XORIS (env reg1) (env reg2) imm + NEG reg1 reg2 -> NEG (env reg1) (env reg2) + NOT reg1 reg2 -> NOT (env reg1) (env reg2) SLW reg1 reg2 ri -> SLW (env reg1) (env reg2) (fixRI ri) SRW reg1 reg2 ri -> SRW (env reg1) (env reg2) (fixRI ri) SRAW reg1 reg2 ri -> SRAW (env reg1) (env reg2) (fixRI ri) - NEG reg1 reg2 -> NEG (env reg1) (env reg2) - NOT reg1 reg2 -> NOT (env reg1) (env reg2) FADD sz r1 r2 r3 -> FADD sz (env r1) (env r2) (env r3) FSUB sz r1 r2 r3 -> FSUB sz (env r1) (env r2) (env r3) FMUL sz r1 r2 r3 -> FMUL sz (env r1) (env r2) (env r3) FDIV sz r1 r2 r3 -> FDIV sz (env r1) (env r2) (env r3) + FNEG r1 r2 -> FNEG (env r1) (env r2) FCMP r1 r2 -> FCMP (env r1) (env r2) + FCTIWZ r1 r2 -> FCTIWZ (env r1) (env r2) _ -> instr where fixAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2) @@ -906,23 +917,23 @@ spillReg vreg_to_slot_map delta dyn vreg {-I386: spill above stack pointer leaving 3 words/spill-} ,IF_ARCH_i386 ( let off_w = (off-delta) `div` 4 - in case regClass vreg of - RcInteger -> MOV L (OpReg dyn) (OpAddr (spRel off_w)) - _ -> GST F80 dyn (spRel off_w) -- RcFloat/RcDouble + in case regClass vreg of { + RcInteger -> MOV L (OpReg dyn) (OpAddr (spRel off_w)); + _ -> GST F80 dyn (spRel off_w)} {- RcFloat/RcDouble -} {-SPARC: spill below frame pointer leaving 2 words/spill-} ,IF_ARCH_sparc( - let off_w = 1 + (off `div` 4) - sz = case regClass vreg of - RcInteger -> W - RcFloat -> F - RcDouble -> DF + let{off_w = 1 + (off `div` 4); + sz = case regClass vreg of { + RcInteger -> W; + RcFloat -> F; + RcDouble -> DF}} in ST sz dyn (fpRel (- off_w)) ,IF_ARCH_powerpc( - let sz = case regClass vreg of - RcInteger -> W - RcFloat -> F - RcDouble -> DF + let{sz = case regClass vreg of { + RcInteger -> W; + RcFloat -> F; + RcDouble -> DF}} in ST sz dyn (AddrRegImm sp (ImmInt (off-delta))) ,)))) @@ -935,22 +946,22 @@ loadReg vreg_to_slot_map delta vreg dyn IF_ARCH_alpha( LD sz dyn (spRel (- (off `div` 8))) ,IF_ARCH_i386 ( let off_w = (off-delta) `div` 4 - in case regClass vreg of - RcInteger -> MOV L (OpAddr (spRel off_w)) (OpReg dyn) - _ -> GLD F80 (spRel off_w) dyn -- RcFloat/RcDouble + in case regClass vreg of { + RcInteger -> MOV L (OpAddr (spRel off_w)) (OpReg dyn); + _ -> GLD F80 (spRel off_w) dyn} {- RcFloat/RcDouble -} ,IF_ARCH_sparc( - let off_w = 1 + (off `div` 4) - sz = case regClass vreg of - RcInteger -> W - RcFloat -> F - RcDouble -> DF + let{off_w = 1 + (off `div` 4); + sz = case regClass vreg of { + RcInteger -> W; + RcFloat -> F; + RcDouble -> DF}} in LD sz (fpRel (- off_w)) dyn ,IF_ARCH_powerpc( - let sz = case regClass vreg of - RcInteger -> W - RcFloat -> F - RcDouble -> DF + let{sz = case regClass vreg of { + RcInteger -> W; + RcFloat -> F; + RcDouble -> DF}} in LD sz dyn (AddrRegImm sp (ImmInt (off-delta))) ,)))) \end{code}