X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=ghc%2Fincludes%2FMachRegs.h;h=5cc6109165f1fcc7f27a2776d15b2ef8fb532911;hb=b8598510c6f7138eeadfc749ec237d9b15df9696;hp=16d429ad63ff8a749fd6477ef364b53863f60ef2;hpb=f6692611aad945e46ffb615bde1df7def3fc742f;p=ghc-hetmet.git

diff --git a/ghc/includes/MachRegs.h b/ghc/includes/MachRegs.h
index 16d429a..5cc6109 100644
--- a/ghc/includes/MachRegs.h
+++ b/ghc/includes/MachRegs.h
@@ -1,5 +1,5 @@
 /* -----------------------------------------------------------------------------
- * $Id: MachRegs.h,v 1.6 1999/11/02 15:05:50 simonmar Exp $
+ * $Id: MachRegs.h,v 1.12 2002/10/02 09:08:44 wolfgang Exp $
  *
  * (c) The GHC Team, 1998-1999
  *
@@ -374,13 +374,13 @@
 #define REG_R7    	r20
 #define REG_R8    	r21
 
-#define REG_F1		fr14
-#define REG_F2		fr15
-#define REG_F3		fr16
-#define REG_F4		fr17
+#define REG_F1		f14
+#define REG_F2		f15
+#define REG_F3		f16
+#define REG_F4		f17
 
-#define REG_D1		fr18
-#define REG_D2		fr19
+#define REG_D1		f18
+#define REG_D2		f19
 
 #define REG_Sp    	r22
 #define REG_Su    	r23
@@ -389,9 +389,57 @@
 #define REG_Hp	    	r25
 #define REG_HpLim	r26
 
+#define NCG_SpillTmp_I1	r27
+#define NCG_SpillTmp_I2	r28
+
+#define NCG_SpillTmp_D1	f20
+#define NCG_SpillTmp_D2	f21
+
 #endif /* powerpc */
 
 /* -----------------------------------------------------------------------------
+   The IA64 register mapping
+
+   We place the general registers in the locals area of the register stack,
+   so that the call mechanism takes care of saving them for us.  We reserve
+   the first 16 for gcc's use - since gcc uses the highest used register to
+   determine the register stack frame size, this gives us a constant size
+   register stack frame.
+   
+   \tr{f16-f32} are the callee-saved floating point registers.
+   -------------------------------------------------------------------------- */
+
+#ifdef ia64_TARGET_ARCH
+
+#define REG(x) __asm__(#x)
+
+#define REG_R1		loc16
+#define REG_R2		loc17
+#define REG_R3		loc18
+#define REG_R4		loc19
+#define REG_R5		loc20
+#define REG_R6		loc21
+#define REG_R7		loc22
+#define REG_R8		loc23
+
+#define REG_F1		f16
+#define REG_F2		f17
+#define REG_F3		f18
+#define REG_F4		f19
+
+#define REG_D1		f20
+#define REG_D2		f21
+
+#define REG_Sp		loc24
+#define REG_Su		loc25
+#define REG_SpLim	loc26
+
+#define REG_Hp		loc27
+#define REG_HpLim	loc28
+
+#endif /* ia64 */
+
+/* -----------------------------------------------------------------------------
    The Sun SPARC register mapping
 
    The SPARC register (window) story: Remember, within the Haskell
@@ -414,6 +462,37 @@
    Note: %g3 is *definitely* clobbered in the builtin divide code (and
    our save/restore machinery is NOT GOOD ENOUGH for that); discretion
    being the better part of valor, we also don't take %g4.
+
+   The paired nature of the floating point registers causes complications for
+   the native code generator.  For convenience, we pretend that the first 22
+   fp regs %f0 .. %f21 are actually 11 double regs, and the remaining 10 are
+   float (single) regs.  The NCG acts accordingly.  That means that the 
+   following FP assignment is rather fragile, and should only be changed
+   with extreme care.  The current scheme is:
+
+      %f0 /%f1    FP return from C
+      %f2 /%f3    D1
+      %f4 /%f5    D2
+      %f6 /%f7    ncg double spill tmp #1
+      %f8 /%f9    ncg double spill tmp #2
+      %f10/%f11   allocatable
+      %f12/%f13   allocatable
+      %f14/%f15   allocatable
+      %f16/%f17   allocatable
+      %f18/%f19   allocatable
+      %f20/%f21   allocatable
+
+      %f22        F1
+      %f23        F2
+      %f24        F3
+      %f25        F4
+      %f26        ncg single spill tmp #1
+      %f27        ncg single spill tmp #2
+      %f28        allocatable
+      %f29        allocatable
+      %f30        allocatable
+      %f31        allocatable
+
    -------------------------------------------------------------------------- */
 
 #if sparc_TARGET_ARCH
@@ -438,12 +517,12 @@
 #define REG_R7    	l7
 #define REG_R8		i5
 
-#define REG_F1	    	f2
-#define REG_F2	    	f3
-#define REG_F3	    	f4
-#define REG_F4	    	f5
-#define REG_D1	    	f6
-#define REG_D2	    	f8
+#define REG_F1	    	f22
+#define REG_F2	    	f23
+#define REG_F3	    	f24
+#define REG_F4	    	f25
+#define REG_D1	    	f2
+#define REG_D2	    	f4
 
 #define REG_Sp    	i0
 #define REG_Su    	i1
@@ -452,12 +531,14 @@
 #define REG_Hp	    	i3
 #define REG_HpLim	i4
 
-#define NCG_Reserved_I1	g1
-#define NCG_Reserved_I2	g2
-#define NCG_Reserved_F1	f14
-#define NCG_Reserved_F2 f15
-#define NCG_Reserved_D1	f16
-#define NCG_Reserved_D2	f18
+#define NCG_SpillTmp_I1	g1
+#define NCG_SpillTmp_I2	g2
+#define NCG_SpillTmp_F1	f26
+#define NCG_SpillTmp_F2 f27
+#define NCG_SpillTmp_D1	f6
+#define NCG_SpillTmp_D2	f8
+
+#define NCG_FirstFloatReg f22
 
 #endif /* sparc */