X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=includes%2FSMP.h;h=49bc336f9985aed40972e3f07e6c20b3508b4f28;hb=dc01512f14cc4710d1f6a7448e642cd11e5e3efe;hp=bf23e0826092a9fc69341a18281b1c08461b9675;hpb=9d5c9fb05b4f05d803a437cba18581d562793f43;p=ghc-hetmet.git

diff --git a/includes/SMP.h b/includes/SMP.h
index bf23e08..49bc336 100644
--- a/includes/SMP.h
+++ b/includes/SMP.h
@@ -60,6 +60,11 @@ EXTERN_INLINE StgWord cas(StgVolatilePtr p, StgWord o, StgWord n);
  */ 
 EXTERN_INLINE void write_barrier(void);
 
+/*
+ * Prevents loads from moving before earlier stores.
+ */
+EXTERN_INLINE void store_load_barrier(void);
+
 /* ----------------------------------------------------------------------------
    Implementations
    ------------------------------------------------------------------------- */
@@ -180,11 +185,31 @@ write_barrier(void) {
 #endif
 }
 
+EXTERN_INLINE void
+store_load_barrier(void) {
+#if i386_HOST_ARCH
+    __asm__ __volatile__ ("lock; addl $0,0(%%esp)" : : : "memory");
+#elif x86_64_HOST_ARCH
+    __asm__ __volatile__ ("lock; addq $0,0(%%rsp)" : : : "memory");
+#elif powerpc_HOST_ARCH
+    __asm__ __volatile__ ("msync" : : : "memory");
+#elif sparc_HOST_ARCH
+    /* Sparc in TSO mode does not require write/write barriers. */
+    __asm__ __volatile__ ("membar" : : : "memory");
+#elif !defined(WITHSMP)
+    return;
+#else
+#error memory barriers unimplemented on this architecture
+#endif
+}
+
 /* ---------------------------------------------------------------------- */
 #else /* !THREADED_RTS */
 
 #define write_barrier() /* nothing */
 
+#define store_load_barrier() /* nothing */
+
 INLINE_HEADER StgWord
 xchg(StgPtr p, StgWord w)
 {
@@ -193,6 +218,17 @@ xchg(StgPtr p, StgWord w)
     return old;
 }
 
+STATIC_INLINE StgWord
+cas(StgVolatilePtr p, StgWord o, StgWord n)
+{
+    StgWord result;
+    result = *p;
+    if (result == o) {
+        *p = n;
+    }
+    return result;
+}
+
 #endif /* !THREADED_RTS */
 
 #endif /* SMP_H */