X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=includes%2FSMP.h;h=ac98feb7a3c2c7e55fd09e1567545ea9b3de2ee8;hb=43d01ce6e6b2bcc4211ee350eb11dec926e38964;hp=223f1581a3963c045b80ae1dc9f2ffe6bf8bb9e0;hpb=c83d2d16d72825ea5ef9a1b3c7096fc9e19491b7;p=ghc-hetmet.git

diff --git a/includes/SMP.h b/includes/SMP.h
index 223f158..ac98feb 100644
--- a/includes/SMP.h
+++ b/includes/SMP.h
@@ -179,7 +179,7 @@ write_barrier(void) {
 #elif powerpc_HOST_ARCH
     __asm__ __volatile__ ("lwsync" : : : "memory");
 #elif sparc_HOST_ARCH
-    /* Sparc in TSO mode does not require write/write barriers. */
+    /* Sparc in TSO mode does not require store/store barriers. */
     __asm__ __volatile__ ("" : : : "memory");
 #elif !defined(WITHSMP)
     return;
@@ -197,8 +197,7 @@ store_load_barrier(void) {
 #elif powerpc_HOST_ARCH
     __asm__ __volatile__ ("sync" : : : "memory");
 #elif sparc_HOST_ARCH
-    /* Sparc in TSO mode does not require write/write barriers. */
-    __asm__ __volatile__ ("membar" : : : "memory");
+    __asm__ __volatile__ ("membar #StoreLoad" : : : "memory");
 #elif !defined(WITHSMP)
     return;
 #else
@@ -215,7 +214,7 @@ load_load_barrier(void) {
 #elif powerpc_HOST_ARCH
     __asm__ __volatile__ ("lwsync" : : : "memory");
 #elif sparc_HOST_ARCH
-    /* Sparc in TSO mode does not require write/write barriers. */
+    /* Sparc in TSO mode does not require load/load barriers. */
     __asm__ __volatile__ ("" : : : "memory");
 #elif !defined(WITHSMP)
     return;