X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=ships%2FDRAM.ship;h=161928e6d593b8bb7ab0df1dcd23fd0219209410;hb=aee85d3dd0435554e14e03b97f268752843a441f;hp=322c3c152131b36abc18e3eacb716f00c5457cc3;hpb=2b139619ed94fd3d45d48882ba5a64e5731e2529;p=fleet.git

diff --git a/ships/DRAM.ship b/ships/DRAM.ship
index 322c3c1..161928e 100644
--- a/ships/DRAM.ship
+++ b/ships/DRAM.ship
@@ -29,31 +29,19 @@ percolate inout:         ddr1_DQ            32
 == FPGA ==============================================================
 
   wire  [31:0]  dram_addr;
-  wire          dram_addr_r_;
+  wire  [31:0]  dram_addr__;
+
   wire          dram_addr_a;
-  wire          dram_isread_;
-  wire  [63:0]  dram_write_data_;
-  wire          dram_write_data_push_;
-  wire          dram_write_data_full;
-  wire   [63:0] dram_read_data;
-  wire          dram_read_data_pop_;
-  wire          dram_read_data_empty;
-  wire   [1:0]  dram_read_data_latency;
-
-  reg         dram_addr_r;
-  reg         dram_isread;
-  reg         dram_write_data_push;
-  reg         dram_read_data_pop;
+  wire  [63:0]  dram_write_data;
+  wire  [63:0]  dram_read_data;
+
+  reg           dram_addr_r;
+  reg           dram_isread;
+
+  assign dram_addr__ = dram_isread ? inAddrRead_d[31:0] : inAddrWrite_d[31:0];
+  assign dram_addr   = { dram_addr__[30:6], 1'b0, dram_addr__[5:0] };
+
   reg  [`WORDWIDTH:0]  out_d;
-  wire [31:0] dram_addr__;
-
-  assign dram_addr_r_ = dram_addr_r;
-  assign dram_isread_ = dram_isread;
-  assign dram_addr__ = !dram_isread ? inAddrWrite_d[31:0] : inAddrRead_d[31:0];
-  assign dram_addr_  = { dram_addr__[30:6], 1'b0, dram_addr__[5:0] };
-  assign dram_write_data_push_ = dram_write_data_push;
-  assign dram_read_data_pop_ = dram_read_data_pop;
-  assign dram_write_data_ = inDataWrite_d;
   assign out_d_ = out_d;
 
    ddr_ctrl 
@@ -78,7 +66,7 @@ percolate inout:         ddr1_DQ            32
           .ddr_cke( ddr1_CE_pin ),
    
           .clk(clk),
-          .reset(!sys_rst_pin),
+          .reset(rst),
           .rot(3'b100),
    
           .fml_wr(!dram_isread && dram_addr_r),
@@ -92,14 +80,12 @@ percolate inout:         ddr1_DQ            32
 
   always @(posedge clk) begin
 
-    if (!rst) begin
+    if (rst) begin
       `reset
       dram_isread <= 0;
       dram_addr_r <= 0;
-      dram_read_data_pop <= 0;
 
     end else begin
-      `flush
       `cleanup
 
       if (dram_addr_r && !dram_addr_a) begin
@@ -128,6 +114,40 @@ percolate inout:         ddr1_DQ            32
 
 == Test ========================================================
 #skip
+// expected output
+#expect 10
+
+// ships required in order to run this code
+#ship debug          : Debug
+#ship memory         : DRAM
+
+memory.inAddrWrite:
+  set word=0;
+  deliver;
+  deliver;
+
+memory.inDataWrite:
+  set word=-1;
+  deliver;
+  set word=-1;
+  deliver;
+
+memory.inAddrRead:
+  recv token;
+  set word=0;
+  deliver;
+
+memory.out:
+  collect;
+  collect;
+  send token to memory.inAddrRead;
+  collect;
+  send to debug.in;
+
+debug.in:
+  set ilc=*;
+  recv, deliver;
+
 
 == Constants ========================================================