X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=ships%2FDebug.ship;h=f79644679545dc9d12aac6f742a3b1cc97ea9a90;hb=c5694a7c8c82fb7d5c424a168fedc8f55f1c32ab;hp=aaeff49e7c731a908f06f06dbb3e1d21476fb0b6;hpb=56553c511a9c2a6d110095ea7ca7c860fa7a31c5;p=fleet.git diff --git a/ships/Debug.ship b/ships/Debug.ship index aaeff49..f796446 100644 --- a/ships/Debug.ship +++ b/ships/Debug.ship @@ -1,40 +1,225 @@ ship: Debug == Ports =========================================================== -data in: data +data in: in +dockless out: out + +percolate down: uart_in 1 +percolate up: uart_out 1 +percolate up: rst_out 1 +percolate down: rst_in 1 == Constants ======================================================== == TeX ============================================================== +percolate up: uart_rts 1 +percolate down: uart_cts 1 + +This ship is used for debugging. It has only one port, {\tt in}. +Programmers should send debug report values to this port. How such +values are reported back to the programmer doing the debugging is left +unspecified. + +\subsection*{To Do} + +Provide an {\tt inOp} port and use opcode ports \cite{am25} to +effectively allow multiple independent ``debug streams'' + +Provide a way to programmatically read back the output of the debug +ship. + == Fleeterpreter ==================================================== public void service() { - if (box_data.dataReadyForShip()) - ((Interpreter)getFleet()).debug(box_data.removeDataForShip()); + if (box_in.dataReadyForShip()) + ((Interpreter)getFleet()).debug(new BitVector(37).set(box_in.removeDataForShip())); } -== ArchSim ============================================================== +== FleetSim ============================================================== == FPGA ============================================================== -`include "macros.v" -module debug (clk, data_debug_data_r, data_debug_data_a, data_debug_data, - data_debug_out_r, data_debug_out_a, data_debug_out ); - input clk; + wire break_i; + reg send_k; + initial send_k = 0; + + reg [`WORDWIDTH-1:0] data_to_host_full_word; + reg [7:0] count_in; + reg [7:0] count_out; + reg [49:0] out_d; + assign out_d_ = out_d; + + wire data_to_host_full; + reg [7:0] data_to_host; + wire data_to_fleet_empty; + wire [7:0] data_to_fleet; + reg data_to_host_write_enable; + reg data_to_fleet_read_enable; + reg [7:0] force_reset; + + wire sio_ce; + wire sio_ce_x4; + + wire break; + wire uart_cts; + assign uart_cts = 0; + assign rst_out = rst_in || (force_reset!=0) /* || break */; + + // fst=3 means clock divider is 3+2=5 for a 50Mhz clock => 10Mhz + // using a 33Mhz clock, + // 33.333Mhz / 38400hz * 4 = 217.013 => 215+2,1 => 215,1 + // using a 100Mhz clock, + // 100Mhz / 38400hz * 4 = 651.039 => 215+2,3 => 215,3 + // using a 100Mhz clock, 115200baud + // 100Mhz / 115200hz * 4 = 217.013 => 215+2,1 => 215,1 +// sasc_brg sasc_brg(clk, !rst_in, 215, 3, sio_ce, sio_ce_x4); + sasc_brg sasc_brg(clk, !rst_in, 215, 1, sio_ce, sio_ce_x4); + sasc_top sasc_top(clk, !rst_in, + uart_in, + uart_out, + uart_cts, + uart_rts, + sio_ce, + sio_ce_x4, + data_to_host, + data_to_fleet, + data_to_fleet_read_enable, + data_to_host_write_enable, + data_to_host_full, + data_to_fleet_empty, + break, + break_i); + + reg [16:0] credits; + + // fpga -> host + always @(posedge clk) begin + if (rst_in /* || break */) begin + count_in <= 0; + count_out <= 0; + force_reset <= 0; + credits = 0; + `reset + end else begin + + `cleanup + + // fpga -> host + data_to_host_write_enable <= 0; + if (force_reset == 1) begin + force_reset <= 0; + data_to_host_write_enable <= 1; + credits = 0; + count_in <= 0; + count_out <= 0; + `reset + end else if (force_reset != 0) begin + force_reset <= force_reset-1; + end else if (count_out==0 && `in_full) begin + `drain_in + data_to_host_full_word <= in_d; + count_out <= 8; + end else if (count_out!=0 && !data_to_host_full && !data_to_host_write_enable && credits!=0) begin + data_to_host <= { 2'b0, data_to_host_full_word[5:0] }; + data_to_host_full_word <= (data_to_host_full_word >> 6); + data_to_host_write_enable <= 1; + count_out <= count_out-1; + credits = credits - 1; + end + + // host -> fpga + data_to_fleet_read_enable <= 0; + if (!data_to_fleet_empty && !data_to_fleet_read_enable) begin + + // Note: if the switch fabric refuses to accept a new item, + // we can get deadlocked in a state where sending a reset + // code (2'b11) won't have any effect. Probably need to go + // back to using the break signal. + + // command 0: data + if (data_to_fleet[7:6] == 2'b00 && `out_empty) begin + data_to_fleet_read_enable <= 1; + out_d <= { out_d[43:0], data_to_fleet[5:0] }; + if (count_in==9) begin + count_in <= 0; + `fill_out + end else begin + count_in <= count_in+1; + end + + // command 1: flow control credit + end else if (data_to_fleet[7:6] == 2'b01) begin + data_to_fleet_read_enable <= 1; + credits = credits + data_to_fleet[5:0]; + +/* + // uncommenting this requires changing data_to_host_write_enable + // to a blocking assignment, and seems to cause data loss whenever + // more than four items are in flight. + // command 2: echo + end else if (data_to_fleet[7:6] == 2'b10 && !data_to_host_full && !data_to_host_write_enable) begin + data_to_fleet_read_enable <= 1; + data_to_host <= data_to_fleet; + data_to_host_write_enable = 1; +*/ + + // command 3: reset (and echo back reset code) + end else if (data_to_fleet[7:6] == 2'b11) begin + data_to_fleet_read_enable <= 1; + data_to_host <= data_to_fleet; + force_reset <= 255; + + end + + end + + end + end + +== UCF ================================================================= + +Net clk_pin LOC=AH15; +Net clk_pin PERIOD = 10 ns HIGH 50%; # 100Mhz + +# 33mhz clock +#Net clk_pin LOC=AH17; +#Net clk_pin TNM_NET = clk_pin; +#TIMESPEC TS_clk_pin = PERIOD clk_pin 30 ns HIGH 50%; # 33Mhz + +Net rst_pin LOC=E9; +Net rst_pin PULLUP; +Net rst_pin TIG; + +#Net uart_cts LOC=G6; +#Net uart_cts IOSTANDARD = LVCMOS33; +#Net uart_cts TIG; + +#Net uart_rts LOC=F6; +#Net uart_rts IOSTANDARD = LVCMOS33; +#Net uart_rts TIG; + +Net uart_in LOC=AG15; +#Net uart_in IOSTANDARD = LVCMOS33; +Net uart_in TIG; +Net uart_in PULLUP; + +Net uart_out LOC=AG20; +#Net uart_out IOSTANDARD = LVCMOS33; +Net uart_out TIG; +Net uart_out PULLUP; + + + - input data_debug_data_r; - output data_debug_data_a; - input [`DATAWIDTH:0] data_debug_data; - output data_debug_out_r; - input data_debug_out_a; - output [`DATAWIDTH:0] data_debug_out; +== Test ================================================================ +#expect 25 - assign data_debug_out_r = data_debug_data_r; - assign data_debug_data_a = data_debug_out_a; - assign data_debug_out = data_debug_data; +#ship debug : Debug -endmodule +debug.in: + set word= 25; + deliver; == Contributors ========================================================= Adam Megacz