X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=ships%2FLut3.ship;h=a85b8f3dd21cf438c08c81f807bf6e1dba7e2f40;hb=aee85d3dd0435554e14e03b97f268752843a441f;hp=c6f39cfee8e8abbc4640b09785351a74d9139511;hpb=edc9d72e3f4d19734fc75c399b56a089dae6504c;p=fleet.git

diff --git a/ships/Lut3.ship b/ships/Lut3.ship
index c6f39cf..a85b8f3 100644
--- a/ships/Lut3.ship
+++ b/ships/Lut3.ship
@@ -18,9 +18,9 @@ NOR
 
 == TeX ==============================================================
 
-This ship implements a 3-input {\bf L}ook {\bf U}p {\bf T}able.  The
-least significant eight bits of the {\tt inLut} value form a truth
-table with three inputs and one output.
+This ship implements a bitwise 3-input {\bf L}ook {\bf U}p {\bf
+T}able.  The least significant eight bits of the {\tt inLut} value
+form a truth table with three inputs and one output.
 
 When values are available at all four inputs they are consumed and a
 value is produced at {\tt out}.  Each bit of {\tt out} is produced by
@@ -34,16 +34,14 @@ bit}.  This three-bit number, ranging from 0 to 7 (decimal), is used
 as a bit index into {\tt inLut}'s value (whose least significant bit
 is considered ``bit zero'').
 
-The ship-specific constants refer to commonly-used truth tables for
-{\it two-input} functions; these constant truth tables are invariant
-under input {\tt in3}.
 
 == Fleeterpreter ====================================================
   public void service() {
       if (box_in1.dataReadyForShip() &&
           box_in2.dataReadyForShip() &&
           box_in3.dataReadyForShip() &&
-          box_inLut.dataReadyForShip()) {
+          box_inLut.dataReadyForShip() &&
+          box_out.readyForDataFromShip()) {
           long a      = box_in1.removeDataForShip();
           long b      = box_in2.removeDataForShip();
           long c      = box_in3.removeDataForShip();
@@ -64,44 +62,34 @@ under input {\tt in3}.
 == FleetSim ==============================================================
 == FPGA ==============================================================
 
-  reg                    have_in1;
-  reg [(`DATAWIDTH-1):0] reg_in1;
-  reg                    have_in2;
-  reg [(`DATAWIDTH-1):0] reg_in2;
-  reg                    have_in3;
-  reg [(`DATAWIDTH-1):0] reg_in3;
-  reg                    have_inLut;
-  reg [(`DATAWIDTH-1):0] reg_inLut;
+  reg          out_draining;
+  wire [7:0]              lut;
 
-  wire [(`DATAWIDTH-1):0] out;
   genvar i;
   generate
-    for(i=0; i<`DATAWIDTH; i=i+1) begin : OUT
-      assign out[i] = inLut_d[{in3_d[i], in2_d[i], in1_d[i]}];
+    for(i=0; i<`WORDWIDTH; i=i+1) begin : OUT
+      assign out_d_[i] = lut[{in3_d[i], in2_d[i], in1_d[i]}];
     end
   endgenerate
 
+  assign lut = inLut_d[7:0];
+
   always @(posedge clk) begin
-    if (!have_in1) begin
-      `onread(in1_r, in1_a) have_in1 = 1; reg_in1 = in1_d; end
-      end
-    if (!have_in2) begin
-      `onread(in2_r, in2_a) have_in2 = 1; reg_in2 = in2_d; end
-      end
-    if (!have_in3) begin
-      `onread(in3_r, in3_a) have_in3 = 1; reg_in3 = in3_d; end
-      end
-    if (!have_inLut) begin
-      `onread(inLut_r, inLut_a) have_inLut = 1; reg_inLut = inLut_d; end
+    if (rst) begin
+      `reset
+      out_draining <= 0;
+    end else begin
+      `cleanup
+      if (out_draining && `out_empty) begin
+         `drain_in1
+         `drain_in2
+         `drain_in3
+         `drain_inLut
+         out_draining <= 0;
       end
-  
-    if (have_in1 && have_in2 && have_in3 && have_inLut) begin
-      out_d = out;
-      `onwrite(out_r, out_a)
-        have_in1  = 0;
-        have_in2  = 0;
-        have_in3  = 0;
-        have_inLut = 0;
+      if (!out_draining && `in1_full && `in2_full && `in3_full && `inLut_full && `out_empty) begin
+         `fill_out
+         out_draining <= 1;
       end
     end
   end
@@ -367,40 +355,48 @@ under input {\tt in3}.
 
 #ship debug        : Debug
 #ship lut          : Lut3
-#ship alu          : Alu1
+#ship alu          : Alu
 
-// constant inputs
-85:          sendto lut.in1;
-51:          sendto lut.in2;
-15:          sendto lut.in3;
-
-lut.in1:   take; [*] deliver;
-lut.in2:   take; [*] deliver;
-lut.in3:   take; [*] deliver;
-lut.inLut: [*] take, deliver;
-lut.out:   [*] take, sendto debug.in;
+lut.in1:   set word= 85; set ilc=*;  deliver;
+lut.in2:   set word= 51; set ilc=*;  deliver;
+lut.in3:   set word= 15; set ilc=*;  deliver;
+lut.out:   set ilc=*;  collect, send to debug.in;
 
 // cycle through truth tables using alu as INC
-1: sendto alu.inOp;
+alu.in2:
+   set word= 1;
+   set ilc=*;  deliver;
 alu.inOp:
-   take;
-   [120] deliver;
-   [120] deliver;
-   [15] deliver;
-alu.in: [*] take, deliver;
-0: sendto alu.in;
+   set word= Alu.inOp[ADD];
+   set ilc=*;  deliver;
+alu.in1:
+   set word= 0;
+   deliver;
+   set ilc=*;  recv, deliver;
 alu.out:
-  [*]  nop;
-  (*) wait, take, sendto lut.inLut;
-  (*) sendto alu.in;
-  kill;
-
-// acks from debug ship trigger new truth tables
-debug.in:   [*] take, deliver, notify alu.out;
+  set olc=2;
+  head;
+  recv token, collect, send to lut.inLut;
+  send to alu.in1;
+  tail;
 
-// kickoff
-0:           sendto lut.inLut;
+lut.inLut:
+  set word= 0;
+  deliver;
+  set ilc=*;  recv, deliver;
 
+// acks from debug ship trigger new truth tables
+debug.in:
+  set ilc=63;
+  recv, deliver, send token to alu.out;
+  set ilc=63;
+  recv, deliver, send token to alu.out;
+  set ilc=63;
+  recv, deliver, send token to alu.out;
+  set ilc=63;
+  recv, deliver, send token to alu.out;
+  set ilc=4;
+  recv, deliver, send token to alu.out;