X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=ships%2FLut3.ship;h=a85b8f3dd21cf438c08c81f807bf6e1dba7e2f40;hb=aee85d3dd0435554e14e03b97f268752843a441f;hp=e6bd469e295bfecb5257938f585ccbf0d46900f9;hpb=11df380a69fbab49049ac267c9099a01d3370e4a;p=fleet.git

diff --git a/ships/Lut3.ship b/ships/Lut3.ship
index e6bd469..a85b8f3 100644
--- a/ships/Lut3.ship
+++ b/ships/Lut3.ship
@@ -62,6 +62,7 @@ is considered ``bit zero'').
 == FleetSim ==============================================================
 == FPGA ==============================================================
 
+  reg          out_draining;
   wire [7:0]              lut;
 
   genvar i;
@@ -74,19 +75,21 @@ is considered ``bit zero'').
   assign lut = inLut_d[7:0];
 
   always @(posedge clk) begin
-    if (!rst) begin
+    if (rst) begin
       `reset
+      out_draining <= 0;
     end else begin
-      `flush
       `cleanup
-      if (`out_draining) begin
+      if (out_draining && `out_empty) begin
          `drain_in1
          `drain_in2
          `drain_in3
          `drain_inLut
+         out_draining <= 0;
       end
-      if (`in1_full && `in2_full && `in3_full && `inLut_full && `out_empty) begin
+      if (!out_draining && `in1_full && `in2_full && `in3_full && `inLut_full && `out_empty) begin
          `fill_out
+         out_draining <= 1;
       end
     end
   end
@@ -372,8 +375,9 @@ alu.in1:
    set ilc=*;  recv, deliver;
 alu.out:
   set olc=2;
-  [Rq] recv token, collect, send to lut.inLut;
-  [Rq] send to alu.in1;
+  head;
+  recv token, collect, send to lut.inLut;
+  send to alu.in1;
   tail;
 
 lut.inLut: