X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=ships%2FLut3.ship;h=a85b8f3dd21cf438c08c81f807bf6e1dba7e2f40;hb=b1638574f882069f08c93445e6d7ce88c44c793b;hp=7781444b5536477102a4f3061710ee30b959c7c0;hpb=218dad65bcc1ce9d386cc858d2e2da9110c6da58;p=fleet.git

diff --git a/ships/Lut3.ship b/ships/Lut3.ship
index 7781444..a85b8f3 100644
--- a/ships/Lut3.ship
+++ b/ships/Lut3.ship
@@ -62,11 +62,12 @@ is considered ``bit zero'').
 == FleetSim ==============================================================
 == FPGA ==============================================================
 
+  reg          out_draining;
   wire [7:0]              lut;
 
   genvar i;
   generate
-    for(i=0; i<`DATAWIDTH; i=i+1) begin : OUT
+    for(i=0; i<`WORDWIDTH; i=i+1) begin : OUT
       assign out_d_[i] = lut[{in3_d[i], in2_d[i], in1_d[i]}];
     end
   endgenerate
@@ -74,22 +75,21 @@ is considered ``bit zero'').
   assign lut = inLut_d[7:0];
 
   always @(posedge clk) begin
-    if (!rst) begin
+    if (rst) begin
       `reset
+      out_draining <= 0;
     end else begin
-      if (!in1_r && in1_a)     in1_a <= 0;
-      if (!in2_r && in2_a)     in2_a <= 0;
-      if (!in3_r && in3_a)     in3_a <= 0;
-      if (!inLut_r && inLut_a) inLut_a <= 0;
-      if (out_r && out_a) begin
-         in1_a <= 1;
-         in2_a <= 1;
-         in3_a <= 1;
-         inLut_a <= 1;
-         out_r <= 0;
+      `cleanup
+      if (out_draining && `out_empty) begin
+         `drain_in1
+         `drain_in2
+         `drain_in3
+         `drain_inLut
+         out_draining <= 0;
       end
-      if (in1_r && !in1_a && in2_r && !in2_a && in3_r && !in3_a && inLut_r && !inLut_a && !out_r && !out_a) begin
-        out_r <= 1;
+      if (!out_draining && `in1_full && `in2_full && `in3_full && `inLut_full && `out_empty) begin
+         `fill_out
+         out_draining <= 1;
       end
     end
   end
@@ -355,47 +355,48 @@ is considered ``bit zero'').
 
 #ship debug        : Debug
 #ship lut          : Lut3
-#ship alu          : Alu2
+#ship alu          : Alu
 
-lut.in1:   literal 85; [*] deliver;
-lut.in2:   literal 51; [*] deliver;
-lut.in3:   literal 15; [*] deliver;
-lut.out:   [*] take, sendto debug.in;
+lut.in1:   set word= 85; set ilc=*;  deliver;
+lut.in2:   set word= 51; set ilc=*;  deliver;
+lut.in3:   set word= 15; set ilc=*;  deliver;
+lut.out:   set ilc=*;  collect, send to debug.in;
 
 // cycle through truth tables using alu as INC
 alu.in2:
-   literal 1;
-   [*] deliver;
+   set word= 1;
+   set ilc=*;  deliver;
 alu.inOp:
-   literal Alu2.inOp[ADD];
-   [*] deliver;
+   set word= Alu.inOp[ADD];
+   set ilc=*;  deliver;
 alu.in1:
-   literal 0;
+   set word= 0;
    deliver;
-   [*] take, deliver;
+   set ilc=*;  recv, deliver;
 alu.out:
-  load loop counter with 2;
-  [L] wait, take, sendto lut.inLut;
-  [L] sendto alu.in1;
+  set olc=2;
+  head;
+  recv token, collect, send to lut.inLut;
+  send to alu.in1;
   tail;
 
 lut.inLut:
-  literal 0;
+  set word= 0;
   deliver;
-  [*] take, deliver;
+  set ilc=*;  recv, deliver;
 
 // acks from debug ship trigger new truth tables
 debug.in:
-  load repeat counter with 63;
-  take, deliver, notify alu.out;
-  load repeat counter with 63;
-  take, deliver, notify alu.out;
-  load repeat counter with 63;
-  take, deliver, notify alu.out;
-  load repeat counter with 63;
-  take, deliver, notify alu.out;
-  load repeat counter with 4;
-  take, deliver, notify alu.out;
+  set ilc=63;
+  recv, deliver, send token to alu.out;
+  set ilc=63;
+  recv, deliver, send token to alu.out;
+  set ilc=63;
+  recv, deliver, send token to alu.out;
+  set ilc=63;
+  recv, deliver, send token to alu.out;
+  set ilc=4;
+  recv, deliver, send token to alu.out;