X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=ships%2FLut3.ship;h=a85b8f3dd21cf438c08c81f807bf6e1dba7e2f40;hb=cbafca81451a452015ea365b3546c3bc0ac7bdbd;hp=7cfd876c5f657a6191320244de8fc9848926b61c;hpb=caa93dc7618f95e403b52ea834fa1f136d26e43d;p=fleet.git

diff --git a/ships/Lut3.ship b/ships/Lut3.ship
index 7cfd876..a85b8f3 100644
--- a/ships/Lut3.ship
+++ b/ships/Lut3.ship
@@ -62,11 +62,12 @@ is considered ``bit zero'').
 == FleetSim ==============================================================
 == FPGA ==============================================================
 
+  reg          out_draining;
   wire [7:0]              lut;
 
   genvar i;
   generate
-    for(i=0; i<`DATAWIDTH; i=i+1) begin : OUT
+    for(i=0; i<`WORDWIDTH; i=i+1) begin : OUT
       assign out_d_[i] = lut[{in3_d[i], in2_d[i], in1_d[i]}];
     end
   endgenerate
@@ -74,19 +75,21 @@ is considered ``bit zero'').
   assign lut = inLut_d[7:0];
 
   always @(posedge clk) begin
-    if (!rst) begin
+    if (rst) begin
       `reset
+      out_draining <= 0;
     end else begin
-      `flush
       `cleanup
-      if (`out_draining) begin
+      if (out_draining && `out_empty) begin
          `drain_in1
          `drain_in2
          `drain_in3
          `drain_inLut
+         out_draining <= 0;
       end
-      if (`in1_full && `in2_full && `in3_full && `inLut_full && `out_empty) begin
+      if (!out_draining && `in1_full && `in2_full && `in3_full && `inLut_full && `out_empty) begin
          `fill_out
+         out_draining <= 1;
       end
     end
   end
@@ -372,8 +375,9 @@ alu.in1:
    set ilc=*;  recv, deliver;
 alu.out:
   set olc=2;
-  [Rq] recv token, collect, send to lut.inLut;
-  [Rq] send to alu.in1;
+  head;
+  recv token, collect, send to lut.inLut;
+  send to alu.in1;
   tail;
 
 lut.inLut: