X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=ships%2FMemory.ship;h=2d1d6f15dbe6abc7fe5b7e02c51d47ebcdfdf943;hb=ecab47750a7599e2193969961c43992c66d2efeb;hp=65a08b06ac0d351790acbc6ae191ac7e9eb3ae10;hpb=686a997301e70a7c249c4bcae7d3e702e2a27f6f;p=fleet.git

diff --git a/ships/Memory.ship b/ships/Memory.ship
index 65a08b0..2d1d6f1 100644
--- a/ships/Memory.ship
+++ b/ships/Memory.ship
@@ -5,8 +5,6 @@ data  in:    inCBD
 data  in:    inAddrRead
 data  in:    inAddrWrite
 data  in:    inDataWrite
-data  in:    inStride
-data  in:    inCount
 
 data  out:   out
 
@@ -14,7 +12,25 @@ data  out:   out
 
 The {\tt Memory} ship represents an interface to a storage space,
 which can be used to read from it or write to it.  This storage space
-might be a fast on-chip cache, off chip DRAM, or perhaps even a disk drive.
+might be a fast on-chip cache, off chip DRAM, or perhaps even a disk
+drive.
+
+Generally, distinct {\tt Memory} ships do not access the same backing
+storage, although this is not strictly prohibited.
+
+Each {\tt Memory} ship may have multiple {\it interfaces}, numbered
+starting with {\tt 0}.  Each interface may have any subset of the
+following docks: {\tt inCBD}, {\tt inAddrRead}, {\tt inAddrWrite},
+{\tt inDataWrite}, and {\tt out}.  If {\tt inCBD} or {\tt inAddrRead}
+is present on an interface, then {\tt out} must be present as well.
+If {\tt inAddrWrite} is present then {\tt inDataWrite} must be present
+as well.
+
+Each interface serializes the operations presented to it; this means
+that an interface with both read and write capabilities will not be
+able to read and write concurrently.  Instead, a {\tt Memory} ship
+with the ability to read and write concurrently should have two
+interfaces, one which is read-only and one which is write-only.
 
 There may be multiple {\tt Memory} ships which interface to the same
 physical storage space.  An implementation of Fleet must provide
@@ -46,7 +62,8 @@ inCount=size}.
 \subsection*{Reading}
 
 When a word is delivered to {\tt inAddrRead}, the word residing in
-memory at that address is provided at {\tt out}.
+memory at that address is provided at {\tt out}.  The {\tt c-flag} at
+the {\tt out} port is set to zero.
 
 \subsection*{Writing}
 
@@ -54,7 +71,8 @@ When a word is delivered to {\tt inAddrWrite} and {\tt inDataWrite},
 the word at {\tt inDataWrite} is written to the address specified by
 {\tt inAddrWrite}.  Once the word is successfully committed to memory,
 the value {\tt inAddr+inStride} is provided at {\tt out} (that is, the
-address of the next word to be written).
+address of the next word to be written).  The {\tt c-flag} at
+the {\tt out} port is set to one.
 
 \subsection*{To Do}
 
@@ -78,7 +96,7 @@ sequence guarantee problem mentioned in the previous paragraph.
 
 == Fleeterpreter ====================================================
     private long[] mem = new long[0];
-    public long readMem(int addr) { return mem[addr]; }
+    public long readMem(int addr) { return addr >= mem.length ? 0 : mem[addr]; }
     public void writeMem(int addr, long val) {
         if (addr >= mem.length) {
             long[] newmem = new long[addr * 2 + 1];
@@ -87,317 +105,141 @@ sequence guarantee problem mentioned in the previous paragraph.
         }
         mem[addr] = val;
     }
-
-    public void dispatch(int addr, int size) {
-        for(int i=addr; i<addr+size; i++) {
-            Instruction instr = ((Interpreter)getFleet()).readInstruction(readMem(i));
-            ((Interpreter)getFleet()).dispatch(instr, i);
-        }
-    }
-
-    public void boot(byte[] instructions) {
-        Interpreter fleet = (Interpreter)getFleet();
-        // load the iscratch and take note of the 0-address INCBD
-        long launch = 0;
-        for(int i=0; i<instructions.length; i+=6) {
-            long word = 0;
-            for(int j=0; j<6; j++)
-                word = (word << 8) | (instructions[i+j] & 0xff);
-            writeMem(i/6, word);
-            if (i==0) launch = word;
-        }
-
-        // dispatch the 0-address INCBD
-        int base = (int)(launch >> 6);
-        base = base & ~(0xffffffff << 18);
-        int size = (int)launch;
-        size = size & ~(0xffffffff <<  6);
-        dispatch(base, size);
+    private Queue<Long> toDispatch = new LinkedList<Long>();
+    public void reset() {
+      super.reset();
+      mem = new long[0];
+      toDispatch.clear();
     }
-
-    private long stride = 0;
-    private long count = 0;
-    private long addr = 0;
-    private boolean writing = false;
-
     public void service() {
+        if (toDispatch.size() > 0) {
+            if (!box_out.readyForDataFromShip()) return;
+            box_out.addDataFromShip(toDispatch.remove());
+        }
         if (box_inCBD.dataReadyForShip()) {
             long val = box_inCBD.removeDataForShip();
-            long addr = val >> 6;
-            long size = val & 0x3f;
-            dispatch((int)addr, (int)size);
-        }
-        if (count > 0) {
-            if (writing) {
-              if (box_inDataWrite.dataReadyForShip() && box_out.readyForDataFromShip()) {
-                 writeMem((int)addr, box_inDataWrite.removeDataForShip());
-                 box_out.addDataFromShip(0);
-                 count--;
-                 addr += stride;
-              }
-            } else {
-              if (box_out.readyForDataFromShip()) {
-                 box_out.addDataFromShip(readMem((int)addr));
-                 count--;
-                 addr += stride;
-              }
-            }
-
-        } else if (box_inAddrRead.dataReadyForShip()) {
-            addr = box_inAddrRead.removeDataForShip();
-            stride = 0;
-            count = 1;
-            writing = false;
-
-        } else if (box_inAddrWrite.dataReadyForShip()) {
-            addr = box_inAddrWrite.peekPacketForShip().value;
-            box_inAddrWrite.removeDataForShip();
-            stride = 0;
-            count = 1;
-            writing = true;
+            long addr = ((Interpreter)getFleet()).CBD_OFFSET.getval(val);
+            long size = ((Interpreter)getFleet()).CBD_SIZE.getval(val);
+            for(int i=0; i<size; i++)
+              toDispatch.add(readMem((int)(addr+i)));
+        } else if (box_inAddrWrite.dataReadyForShip() && box_inDataWrite.dataReadyForShip() && box_out.readyForDataFromShip()) {
+            writeMem((int)box_inAddrWrite.removeDataForShip(), box_inDataWrite.removeDataForShip());
+            box_out.addDataFromShip(0,true);
+        } else if (box_inAddrRead.dataReadyForShip() && box_out.readyForDataFromShip()) {
+            box_out.addDataFromShip(readMem((int)box_inAddrRead.removeDataForShip()),false);
         }
     }
 
 == FleetSim ==============================================================
 
 == FPGA ==============================================================
-`include "macros.v"
-`define BRAM_ADDR_WIDTH 14
-`define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH
-`define BRAM_NAME some_bram
-
-/* bram.inc */
-module `BRAM_NAME(clk, rst, we, a, dpra, di, spo, dpo); 
-    input  clk; 
-    input  rst; 
-    input  we; 
-    input  [(`BRAM_ADDR_WIDTH-1):0] a; 
-    input  [(`BRAM_ADDR_WIDTH-1):0] dpra; 
-    input  [(`BRAM_DATA_WIDTH-1):0] di; 
-    output [(`BRAM_DATA_WIDTH-1):0] spo; 
-    output [(`BRAM_DATA_WIDTH-1):0] dpo; 
-    reg    [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
-    reg    [(`BRAM_ADDR_WIDTH-1):0] read_a; 
-    reg    [(`BRAM_ADDR_WIDTH-1):0] read_dpra; 
-    always @(posedge clk) begin 
-        if (we) 
-            ram[a] <= di; 
-        read_a <= a; 
-        read_dpra <= dpra; 
-    end
-    assign spo = ram[read_a]; 
-    assign dpo = ram[read_dpra]; 
-endmodule 
-/* bram.inc */
-
-module memory (clk, rst,
-               cbd_r,          cbd_a_,         cbd_d,
-               in_addr_r,      in_addr_a_,     in_addr_d,
-               write_addr_r,   write_addr_a_,  write_addr_d,
-               write_data_r,   write_data_a_,  write_data_d,
-               stride_r,       stride_a_,      stride_d,
-               count_r,        count_a_,       count_d,
-               out_r_,         out_a,          out_d_,
-               preload_r,      preload_a_,     preload_d,
-               ihorn_r_,       ihorn_a,        ihorn_d_,
-               dhorn_r_,       dhorn_a,        dhorn_d_
-              );
-
-  input  clk;
-  input  rst;
-  `input(in_addr_r,      in_addr_a,     in_addr_a_,     [(2+`DATAWIDTH-1):0],       in_addr_d)
-  `input(write_addr_r,   write_addr_a,  write_addr_a_,  [(2+`DATAWIDTH-1):0],       write_addr_d)
-  `input(write_data_r,   write_data_a,  write_data_a_,  [(`DATAWIDTH-1):0],         write_data_d)
-  `input(stride_r,       stride_a,      stride_a_,      [(`DATAWIDTH-1):0],         stride_d)
-  `input(count_r,        count_a,       count_a_,       [(`DATAWIDTH-1):0],         count_d)
-  `output(out_r,         out_r_,        out_a,          [(`DATAWIDTH-1):0],         out_d_)
-  `input(preload_r,      preload_a,     preload_a_,     [(`DATAWIDTH-1):0],         preload_d)
-  `input(cbd_r,          cbd_a,         cbd_a_,         [(`DATAWIDTH-1):0],         cbd_d)
-  `output(ihorn_r,       ihorn_r_,      ihorn_a,        [(`PACKET_WIDTH-1):0], ihorn_d_)
-  `defreg(ihorn_d_,                                     [(`PACKET_WIDTH-1):0], ihorn_d)
-  `output(dhorn_r,       dhorn_r_,      dhorn_a,        [(`PACKET_WIDTH-1):0],      dhorn_d_)
-  `defreg(dhorn_d_,                                     [(`PACKET_WIDTH-1):0],      dhorn_d)
-
-  reg ihorn_full;
-  initial ihorn_full = 0;
-  reg dhorn_full;
-  initial dhorn_full = 0;
-  reg command_valid;
-  initial command_valid = 0;
-
-  reg [(`BRAM_ADDR_WIDTH-1):0]    preload_pos;
-  reg [(`BRAM_ADDR_WIDTH-1):0]    preload_size;
-  initial preload_size = 0;
-
-  reg [(`BRAM_ADDR_WIDTH-1):0]    current_instruction_read_from;
-  reg [(`BRAM_ADDR_WIDTH-1):0]    temp_base;
-  reg [(`CODEBAG_SIZE_BITS-1):0]  temp_size;
-  reg [(`BRAM_ADDR_WIDTH-1):0]    cbd_base;
-  reg [(`CODEBAG_SIZE_BITS-1):0]  cbd_size;
-  reg [(`CODEBAG_SIZE_BITS-1):0]  cbd_pos;
-  reg [(`INSTRUCTION_WIDTH-1):0]  command;
-  reg [(`BRAM_DATA_WIDTH-1):0]    ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
-  reg                             send_done;
-  reg                             send_read;
-
-  reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp;
-  reg [(`DATAWIDTH-1):0]                                     data;
 
-  reg                             write_flag;
-  reg [(`BRAM_ADDR_WIDTH-1):0]    in_addr;
-  reg [(`BRAM_DATA_WIDTH-1):0]    write_data;
-
-  wire [(`BRAM_DATA_WIDTH-1):0]   ramread;
-
-  reg command_valid_read;
-  initial command_valid_read = 0;
+  `define BRAM_ADDR_WIDTH 14
+  `define BRAM_SIZE (1<<(`BRAM_ADDR_WIDTH))
 
-  reg launched;
-  initial launched = 0;
+  reg    [(`WORDWIDTH-1):0]       ram [((`BRAM_SIZE)-1):0];
+  reg    [(`BRAM_ADDR_WIDTH-1):0] addr1;
+  reg    [(`BRAM_ADDR_WIDTH-1):0] addr2;
+  reg    [(`WORDWIDTH-1):0]       out1;
+  reg    [(`WORDWIDTH-1):0]       out2;
 
-  some_bram mybram(clk, rst, write_flag, in_addr, current_instruction_read_from, write_data, not_connected, ramread);
-  assign out_d_ = ramread;
-
-  always @(posedge clk /*or negedge rst*/) begin
-
-    if (!rst) begin
-      ihorn_full <= 0;
-      dhorn_full <= 0;
-      command_valid <= 0;
+  reg                             out_w;
+  reg                             write_flag;
+  reg [(`BRAM_ADDR_WIDTH-1):0]    cursor;
+  reg [(`CODEBAG_SIZE_BITS-1):0]  counter;
 
-      // uncommenting either of these causes headaches
-      preload_size <= 0;
-      preload_pos <= 0;
-      temp_base = 0;
-      temp_size = 0;
+  assign out_d_ = { out_w, out1 };
 
-      launched <= 0;
-      command_valid_read <= 0;
-      write_flag <= 0;
+  // I use "blocking assignment" here in order to facilitate BRAM inference
+  always @(posedge clk) begin
+    write_flag = 0;
 
-      dhorn_r <= 0;
-      ihorn_r <= 0;
-      out_r <= 0;
+    if (rst) begin
+      `reset
+      cursor      = 0;
+      counter     = 0;
     end else begin
+      `cleanup
+
+      if (counter!=0) begin
+        if (`out_empty) begin
+          `fill_out
+          out_w    = 0;
+          addr1    = cursor;
+          cursor   = cursor  + 1;
+          counter  = counter - 1;
+        end
 
-    write_flag <= 0;
-
-    if (!in_addr_r && in_addr_a) in_addr_a = 0;
-    if (!write_data_r && write_data_a) write_data_a = 0;
-    if (!write_addr_r && write_addr_a) write_addr_a = 0;
-
-    if (command_valid_read) begin
-      command_valid_read  <= 0;
-      command_valid       <= 1;
-
-    end else  if (send_done) begin
-      `onwrite(out_r, out_a)
-        send_done <= 0;
-      end
-
-    end else  if (send_read) begin
-      `onwrite(out_r, out_a)
-        send_read <= 0;
-      end
-
-    end else if (in_addr_r) begin
-      in_addr_a                        = 1;
-      send_read                       <= 1;
-      current_instruction_read_from   <= in_addr_d[(`DATAWIDTH-1):0];
-
-    end else if (write_addr_r && write_data_r) begin
-      write_addr_a       = 1;
-      write_data_a       = 1;
-      send_done         <= 1;
-      write_flag        <= 1;
-      in_addr           <= write_addr_d[(`DATAWIDTH-1):0];
-      write_data        <= write_data_d;
-
-    end else if (ihorn_full && launched) begin
-      `onwrite(ihorn_r, ihorn_a)
-        ihorn_full <= 0;
-      end
-
-    end else if (dhorn_full) begin
-      `onwrite(dhorn_r, dhorn_a)
-        dhorn_full <= 0;
-      end
-
-    end else if (command_valid) begin
-      command_valid <= 0;
-      command = ramread;
-      ihorn_full  <= 1;
-      `packet_data(ihorn_d) <= `instruction_data(command);
-      `packet_dest(ihorn_d) <= `instruction_dest(command);
-
-    end else if (cbd_pos < cbd_size) begin
-      current_instruction_read_from <= cbd_base+cbd_pos;
-      command_valid_read            <= 1;
-      cbd_pos                       <= cbd_pos + 1;
+      end else if (`inCBD_full) begin
+        cursor    = inCBD_d[(`WORDWIDTH-1):(`CODEBAG_SIZE_BITS)];
+        counter   = inCBD_d[(`CODEBAG_SIZE_BITS-1):0];
+        addr1     = cursor;
+        `drain_inCBD
+
+      end else if (`out_empty && `inAddrRead_full) begin
+        addr1     = inAddrRead_d[(`WORDWIDTH-1):0];
+        `drain_inAddrRead
+        `fill_out
+        out_w     = 0;
+
+      end else if (`out_empty && `inAddrWrite_full && `inDataWrite_full) begin
+        write_flag = 1;
+        `drain_inAddrWrite
+        `drain_inDataWrite
+        `fill_out
+        addr2     = inAddrWrite_d[(`WORDWIDTH-1):0];
+        out_w     = 1;
 
-    end else begin
-      `onread(cbd_r, cbd_a)
-        cbd_pos       <= 0;
-        cbd_size      <= cbd_d[(`CODEBAG_SIZE_BITS-1):0];
-        cbd_base      <= cbd_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)];
-
-      end else begin
-        `onread(preload_r, preload_a)
-          if (preload_size == 0) begin
-            preload_size     <= preload_d;
-            preload_pos      <= 0;
-          end else if (!launched) begin
-            write_flag <= 1;
-            write_data <= preload_d;
-            in_addr <= preload_pos;
-            if (preload_pos == 0) begin
-              temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)];
-              temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0];
-            end
-            if ((preload_pos+1) == preload_size) begin
-              cbd_pos  <= 0;
-              cbd_base <= temp_base;
-              cbd_size <= temp_size;
-              launched <= 1;
-            end
-            preload_pos      <= preload_pos + 1;
-          end
-        end
       end
-
     end
 
-    end
+    // this must appear at the end of the block, outside of any if..then's
+    if (write_flag) 
+      ram[addr2] <= inDataWrite_d; 
+    out1 <= ram[addr1];
+    out2 <= ram[addr2]; 
   end
-endmodule
-
-  
+    
 
 
 
 == Test ==============================================================
+// Note: this only tests the read/write interfaces, not the inCBD interface
+// FIXME: test c-flag at out dock
+
 // expected output
-#expect 12
-#expect 13
-#expect 14
+#expect 10
 
 // ships required in order to run this code
 #ship debug          : Debug
 #ship memory         : Memory
 
-// instructions not in any codebag are part of the "root codebag"
-// which is dispatched when the code is loaded
+memory.inAddrWrite:
+  set word=3;
+  deliver;
+  deliver;
+
+memory.inDataWrite:
+  set word=4;
+  deliver;
+  set word=10;
+  deliver;
 
-memory.inCBD:
-  literal BOB;
+memory.inAddrRead:
+  recv token;
+  set word=3;
   deliver;
 
-BOB: {
-  debug.in:
-    literal 12; deliver;
-    literal 13; deliver;
-    literal 14; deliver;
-}
+memory.out:
+  collect;
+  collect;
+  send token to memory.inAddrRead;
+  collect;
+  send to debug.in;
+
+debug.in:
+  set ilc=*;
+  recv, deliver;
 
 
 == Constants ========================================================