X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=ships%2FMemory.ship;h=42997afc0cf8b9c64111373191c56cc7e7d2d679;hb=56b5406839e38eee604ddc3e645d07c1443fc118;hp=c8cd957089baf05347526dbb726fc70d74d11d55;hpb=7bbbd4be446d1426a2cbc34e61dfb42a6f7cfcaa;p=fleet.git diff --git a/ships/Memory.ship b/ships/Memory.ship index c8cd957..42997af 100644 --- a/ships/Memory.ship +++ b/ships/Memory.ship @@ -75,89 +75,181 @@ data out: out == FPGA ============================================================== `include "macros.v" `define BRAM_ADDR_WIDTH 14 -`define BRAM_DATA_WIDTH `DATAWIDTH -`define BRAM_NAME dscratch_bram +`define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH +`define BRAM_NAME some_bram `include "bram.inc" -module dscratch (clk, - read_addr_r, read_addr_a_, read_addr_d, - read_data_r_, read_data_a, read_data_d_, - write_addr_r, write_addr_a_, write_addr_d, +module memory (clk, + cbd_r, cbd_a_, cbd_d, + in_addr_r, in_addr_a_, in_addr_d, write_data_r, write_data_a_, write_data_d, - write_done_r_, write_done_a, write_done_d_ + stride_r, stride_a_, stride_d, + count_r, count_a_, count_d, + out_r_, out_a, out_d_, + preload_r, preload_a_, preload_d, + ihorn_r_, ihorn_a, ihorn_d_, + dhorn_r_, dhorn_a, dhorn_d_ ); input clk; - `input(read_addr_r, read_addr_a, read_addr_a_, [(`DATAWIDTH-1):0], read_addr_d) - `output(read_data_r, read_data_r_, read_data_a, [(`DATAWIDTH-1):0], read_data_d_) - `defreg(read_data_d_, [(`DATAWIDTH-1):0], read_data_d) - - `input(write_addr_r, write_addr_a, write_addr_a_, [(`DATAWIDTH-1):0], write_addr_d) - `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d) - `output(write_done_r, write_done_r_, write_done_a, [(`DATAWIDTH-1):0], write_done_d_) - `defreg(write_done_d_, [(`DATAWIDTH-1):0], write_done_d) - - reg bram_we; - wire bram_we_; - assign bram_we_ = bram_we; - wire [(`BRAM_DATA_WIDTH-1):0] bram_read_data; - reg [(`BRAM_ADDR_WIDTH-1):0] bram_write_address; - wire [(`BRAM_ADDR_WIDTH-1):0] bram_read_address; - reg [(`BRAM_DATA_WIDTH-1):0] bram_write_data; - wire [(`BRAM_DATA_WIDTH-1):0] bram_write_data_; - assign bram_write_data_ = bram_write_data; - `BRAM_NAME mybram(clk, - bram_we_, bram_write_address, - bram_read_address, bram_write_data_, - not_connected, bram_read_data); - - reg send_done; - - reg have_read; initial have_read = 0; - reg read_pending; initial read_pending = 0; - assign bram_read_address = read_addr_d; + `input(in_addr_r, in_addr_a, in_addr_a_, [(`DATAWIDTH-1):0], in_addr_d) + `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d) + `input(stride_r, stride_a, stride_a_, [(`DATAWIDTH-1):0], stride_d) + `input(count_r, count_a, count_a_, [(`DATAWIDTH-1):0], count_d) + `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_) + `defreg(out_d_, [(`DATAWIDTH-1):0], out_d) + + `input(preload_r, preload_a, preload_a_, [(`DATAWIDTH-1):0], preload_d) + `input(cbd_r, cbd_a, cbd_a_, [(`DATAWIDTH-1):0], cbd_d) + `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_) + `defreg(ihorn_d_, [(`INSTRUCTION_WIDTH-1):0], ihorn_d) + `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_) + `defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d) + + reg ihorn_full; + initial ihorn_full = 0; + reg dhorn_full; + initial dhorn_full = 0; + reg command_valid; + initial command_valid = 0; + + reg [(`BRAM_ADDR_WIDTH-1):0] preload_pos; + reg [(`BRAM_ADDR_WIDTH-1):0] preload_size; + initial preload_size = 0; + + reg [(`BRAM_ADDR_WIDTH-1):0] current_instruction_read_from; + reg [(`BRAM_ADDR_WIDTH-1):0] temp_base; + reg [(`CODEBAG_SIZE_BITS-1):0] temp_size; + reg [(`BRAM_ADDR_WIDTH-1):0] cbd_base; + reg [(`CODEBAG_SIZE_BITS-1):0] cbd_size; + reg [(`CODEBAG_SIZE_BITS-1):0] cbd_pos; + reg [(`INSTRUCTION_WIDTH-1):0] command; + reg [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0]; + reg send_done; + + reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp; + reg [(`DATAWIDTH-1):0] data; + + reg write_flag; + reg [(`BRAM_ADDR_WIDTH-1):0] in_addr; + reg [(`BRAM_DATA_WIDTH-1):0] write_data; + + wire [(`BRAM_DATA_WIDTH-1):0] ramread; + + reg command_valid_read; + initial command_valid_read = 0; + + reg launched; + initial launched = 0; + + some_bram mybram(clk, write_flag, in_addr, current_instruction_read_from, write_data, not_connected, ramread); always @(posedge clk) begin - bram_we = 0; - if (send_done) begin - `onwrite(write_done_r, write_done_a) - send_done = 0; + + write_flag <= 0; + + if (!in_addr_r && in_addr_a) in_addr_a = 0; + if (!write_data_r && write_data_a) write_data_a = 0; + + if (command_valid_read) begin + command_valid_read <= 0; + command_valid <= 1; + + end else if (send_done) begin + `onwrite(out_r, out_a) + send_done <= 0; end - end else begin - if (!write_addr_r && write_addr_a) write_addr_a = 0; - if (!write_data_r && write_data_a) write_data_a = 0; - if (write_addr_r && write_data_r) begin - write_addr_a = 1; - write_data_a = 1; - bram_we = 1; - send_done = 1; - bram_write_address = write_addr_d; - bram_write_data = write_data_d; + + end else if (in_addr_r && write_data_r) begin + in_addr_a = 1; + write_data_a = 1; + send_done <= 1; + write_flag <= 1; + in_addr <= in_addr_d; + write_data <= write_data_d; + + end else if (ihorn_full && launched) begin + `onwrite(ihorn_r, ihorn_a) + ihorn_full <= 0; end - end - if (read_pending) begin - read_pending <= 0; - have_read <= 1; - read_data_d <= bram_read_data; - end else if (have_read) begin - `onwrite(read_data_r, read_data_a) - have_read <= 0; + end else if (dhorn_full) begin + `onwrite(dhorn_r, dhorn_a) + dhorn_full <= 0; end + + end else if (command_valid) begin + command_valid <= 0; + command = ramread; + case (command[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)]) + 0: begin + ihorn_full <= 1; + ihorn_d <= command; + end + 1: begin + dhorn_full <= 1; + temp = command[(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0]; + temp = temp + ( { current_instruction_read_from, {(`CODEBAG_SIZE_BITS){1'b0}} }); + data[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)] = temp; + data[(`CODEBAG_SIZE_BITS-1):0] = command[(`CODEBAG_SIZE_BITS-1):0]; + `packet_data(dhorn_d) <= temp; + `packet_dest(dhorn_d) <= + command[(`INSTRUCTION_WIDTH-3):(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)+1)]; + end + 2: begin + dhorn_full <= 1; + `packet_data(dhorn_d) <= { {(`DATAWIDTH-24){command[23]}}, command[23:0] }; + `packet_dest(dhorn_d) <= command[34:24]; + end + 3: begin + dhorn_full <= 1; + `packet_data(dhorn_d) <= { {(`DATAWIDTH-24){command[23]}}, command[23:0] } + current_instruction_read_from; + `packet_dest(dhorn_d) <= command[34:24]; + end + endcase + + end else if (cbd_pos < cbd_size) begin + current_instruction_read_from <= cbd_base+cbd_pos; + command_valid_read <= 1; + cbd_pos <= cbd_pos + 1; + end else begin - `onread(read_addr_r, read_addr_a) - // ======= Careful with the timing here! ===================== - // We MUST capture bram_read_data on the very next clock since - // read_addr_d is free to change after the next clock - // =========================================================== - read_pending <= 1; + `onread(cbd_r, cbd_a) + cbd_pos <= 0; + cbd_size <= cbd_d[(`CODEBAG_SIZE_BITS-1):0]; + cbd_base <= cbd_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)]; + + end else begin + `onread(preload_r, preload_a) + if (preload_size == 0) begin + preload_size <= preload_d; + end else if (!launched) begin + write_flag <= 1; + write_data <= preload_d; + in_addr <= preload_pos; + if (preload_pos == 0) begin + temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)]; + temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0]; + end + if ((preload_pos+1) == preload_size) begin + cbd_pos <= 0; + cbd_base <= temp_base; + cbd_size <= temp_size; + launched <= 1; + end + preload_pos <= preload_pos + 1; + end + end end end - end - endmodule + + + + + == Constants ======================================================== == TeX ==============================================================