X-Git-Url: http://git.megacz.com/?a=blobdiff_plain;f=src%2Fcom%2Fsun%2Fvlsi%2Fchips%2Fmarina%2Ftest%2FMarinaTest.java;h=42e3486389f223a0dab7b453e6d5ca9d4fbd572e;hb=74c0578c820fde83bddd777a5474c7efc9684e09;hp=91a394428e04b0ed81ff230e106151b8f073f555;hpb=99e1b8eb790bc82e655587bd2ed60ca771328730;p=fleet.git

diff --git a/src/com/sun/vlsi/chips/marina/test/MarinaTest.java b/src/com/sun/vlsi/chips/marina/test/MarinaTest.java
index 91a3944..42e3486 100644
--- a/src/com/sun/vlsi/chips/marina/test/MarinaTest.java
+++ b/src/com/sun/vlsi/chips/marina/test/MarinaTest.java
@@ -34,6 +34,7 @@ import edu.berkeley.fleet.api.Instruction.Set.SetDest;
 import edu.berkeley.fleet.api.Instruction.Set.SetSource;
 import edu.berkeley.fleet.marina.MarinaFleet;
 import edu.berkeley.fleet.marina.MarinaPath;
+import com.sun.async.test.*;
 
 /**
  * Tests for Marina
@@ -214,20 +215,38 @@ public class MarinaTest {
                 fatal(true, "unrecognized CmdArgs.Mode");
                 return;
         }
+
         model = cmdArgs.useVerilog
             ? new VerilogModel()
             : cmdArgs.useHsim
             ? new HsimModel()
+            : cmdArgs.silicon
+            ? new SiliconChip()
             : new NanosimModel();
             
-        ((SimulationModel)model).setOptimizedDirectReadsWrites(true);
+        if (model instanceof SimulationModel)
+            ((SimulationModel)model).setOptimizedDirectReadsWrites(true);
 
         CYCLE_TIME_NS = cmdArgs.useVerilog ? (100*20) : 0.250;
-        int khz   = model instanceof VerilogModel ? 100000 : cmdArgs.jtagShift ? 20000 : 1000000;
-
-        prln("constructing jtag controller");
-        JtagTester tester = ((SimulationModel)model).createJtagTester("TCK", "TMS", "TRSTb", "TDI", "TDO");
-        tester.printInfo = false;
+        int khz   =
+            model instanceof VerilogModel
+            ? 100000
+            : cmdArgs.jtagShift
+            ? 20000
+            : model instanceof ChipModel
+            ? 1
+            : 1000000;
+
+        System.err.println("constructing jtag controller");
+        JtagTester tester =
+            model instanceof SimulationModel
+            ? ((SimulationModel)model).createJtagTester("TCK", "TMS", "TRSTb", "TDI", "TDO")
+            : new Netscan4("jtag3", 2);
+        Logger.setLogInits(true);
+        tester.setLogSets(true);
+        tester.setLogOthers(true);
+        tester.setAllLogging(true);
+        tester.printInfo = true;
 
         ChainControls ccs = new ChainControls();
         PowerChannel pc = new ManualPowerChannel("pc", false);
@@ -274,13 +293,18 @@ public class MarinaTest {
             ((SimulationModel)model).start("verilog", "marina.v", VerilogModel.DUMPVARS, !cmdArgs.jtagShift);
         else if (model instanceof HsimModel)
             ((SimulationModel)model).start("hsim64", netListName, 0, !cmdArgs.jtagShift);
-        else
+        else if (model instanceof NanosimModel)
             ((SimulationModel)model).start("nanosim -c cfg", netListName, 0, !cmdArgs.jtagShift);
+        else
+            {}
         prln("model started");
 
         model.waitNS(1000);
         prln("deasserting master clear");
-        ((SimulationModel)model).setNodeState(Marina.MASTER_CLEAR, 0);
+        if (model instanceof SimulationModel)
+            ((SimulationModel)model).setNodeState(Marina.MASTER_CLEAR, 0);
+        else
+            prln("FIXME: need to deassert master clear");
         model.waitNS(1000);
 
         if (cmdArgs.testNum!=0 && cmdArgs.testNum!=1) {
@@ -289,8 +313,9 @@ public class MarinaTest {
         }
         
         doOneTest(cmdArgs.testNum);
-        
-        ((SimulationModel)model).finish();
+
+        if (model instanceof SimulationModel)
+            ((SimulationModel)model).finish();
     }
     private void doSilicon() {
         model = new SiliconChip();